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Academics

Dimitrios Soudris
   Professor
   9 Heroon Polytechneiou, Zographou Campus

Dimitrios Soudris received his Diploma in Electrical Engineering from the University of Patras, Greece, in 1987. He received the Ph.D. Degree in Electrical Engineering, from the University of Patras in 1992. He was working as a Professor in Dept. of Electrical and Computer Engineering, Democritus University of Thrace for thirteen years since 1995. He is currently working as Associate Professor in School of Electrical and Computer Engineering, Dept. Computer Science of National Technical University of Athens, Greece. His research interests include embedded systems design, reconfigurable architectures, reliability and low power VLSI design. He has published more than 340 papers in international journals and conferences. Also, he is coauthor/coeditor in seven books of Kluwer and Springer. He is leader and principal investigator in numerous research projects funded from the Greek Government and Industry, European Commission (ESPRIT II-III-IV and 5th & 7th IST), ENIAC-JU and European Space Agency. He has served as General Chair and Program Chair for PATMOS 99 and 2000, respectively, General Chair of IFIP-VLSI-SOC 2008 and General Co-Chair of PARMA Workshop 2013. Also, he received an award from INTEL and IBM for the EU project LPGD 25256, awards in ASP-DAC 05 and VLSI 05 for EU AMDREL project IST-2001-34379.

    Books

    • Nikolaos Zompakis ,
    • Michail Noltsis ,
    • Panagiota Nikolaou ,
    • Panagiotis Englezakis ,
    • Zacharias Hadjilambrou ,
    • Lorena Ndreu ,
    • Giuseppe Massari ,
    • Simone Libutti ,
    • Antoni Portero ,
    • Federico Sassi ,
    • Alessandroy Bacchini ,
    • Chrysostomos Nicopoulos ,
    • Yiannakis Sazeides ,
    • Radim Vavrik ,
    • Martin Golasowski ,
    • Jiri Sevcik ,
    • S. Kuchar ,
    • Vit Vondrak ,
    • Agnes Fritsch ,
    • H. Cappelle ,
    • Francky Catthoor ,
    • William Fornaciari and
    • Dimitrios Soudris

    The HARPA approach to ensure dependable performance

    Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms: A Cross-layer Approach DOI: 10.1007/978-3-319-91962-1_1
  • Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms – A Cross-layer Approach

    Springer Publishers DOI: 10.1007/978-3-319-91962-1
  • Hardware Accelerators in Data Centers

    Springer Publishers, 2018. DOI: 10.1007/978-3-319-92792-3 DOI: 10.1007/978-3-319-92792-3
  • CyberPhysical Systems: Decision Making Mechanisms and Applications

    River Publishers 2017
  • Σχεδιασμός ενσωματωμένων συστημάτων

    ISBN: 978-960-9732-20-8
  • Ενσωματωμένα συστήματα: Ο αθέατος ψηφιακός κόσμος

    Κάλιππος
  • Trusted Computing for Embedded Systems

    Springer Publishers, 2015. ISBN 978-3-319-09420-5
    • D. Atienza ,
    • Stylianos Mamagkakis ,
    • C. Poucet ,
    • Miguel Peon ,
    • Alexandros Bartzas ,
    • Francky Catthoor and
    • Dimitrios Soudris

    Dynamic Memory Management for Embedded Systems

    Springer, 2015. ISBN 978-3-319-10571-0, ISBN 978-3-319-10572-7
  • Designing 2D and 3D Network-on-Chip Architectures

    ISBN 978-1-4614-4273-8
  • Scalable Multi-core Architectures: Design Methodologies and Tools

    Springer Science, 2011, ISBN 978-1-4419-6777-0
  • Σχεδίαση ολοκληρωμένων κυκλωμάτων CMOS VLSI(3rd edition)

    Εκδόσεις Παπασωτηρίου 2010
  • VLSI-SOC: Design Methodologies for SoC and SiP

    Springer, Dordrecht/London/Boston, 1st Edition 2010, VIII
  • Three Dimensional System Integration: IC Stacking Process and Design

    Springer Science, April 2010, ISBN-10: 1441909613
  • Fine-and Coarse-Grain Reconfigurable Computing

    Springer, Dordrecht/London/Boston, August 2007, ISBN 978 - 1 - 4020 - 6504 - 0
  • Σχεδιασμός Ολοκληρωμένων Κυκλωμάτων CMOS: Εφαρμογές και Εργαστηριακές Ασκήσεις

    Εκδόσεις Πανεπιστημίου Πατρών
  • Designing CMOS Circuits for Low Power

    Kluwer Academic Publishers, 2002
  • Σχεδίαση ολοκληρωμένων κυκλωμάτων CMOS VLSI

    Εκδόσεις Παπασωτηρίου 1996

    Book Chapters

  • Aging Evaluation and Mitigation Techniques Targeting FPGA Devices

    Low-Power Circuits for Emerging Applications in Communications, Computing, and Sensing, DOI: https://doi.org/10.1201/9780429507564
  • DVFS-oriented scenario applications to processor architectures

    System-Scenario-based Design Principles and Applications, 2019, DOI: 10.1007/978-3-030-20343-6_4
  • System scenario application to dependable system design

    System-Scenario-based Design Principles and Applications, 2019, DOI: 10.1007/978-3-030-20343-6_7
  • Towards Plug&Play Smart Thermostats for Building’s Heating/Cooling Control

    In: Siozios K., Anagnostos D., Soudris D., Kosmatopoulos E. (eds) IoT for Smart Grids. Power Systems. Springer, Cham
      BibTeX
  • “HARPA RT,” book chapter in “Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms – A Cross-layer Approach”

    Springer Publishers
  • “Energy-efficient acceleration of Spark Machine Learning applications on FPGAs,” pp. 91-109, Book Chapter in Christoforos Kachris, Babak Falsafi and Dimitrios Soudris, “Hardware Accelerators in Data Centers”

    Springer Publishers, 2018. DOI: 10.1007/978-3-319-92792-3
  • “Design Space Exploration Methodology Based on Decision Trees for Cyber-Physical Systems,” in Book “Cyber-Physical Systems: Decision Making Mechanisms and Applications”

  • “On Designing Decision-Making Mechanisms for Cyber-Physical Systems” in Book “Cyber-Physical Systems: Decision Making Mechanisms and Applications”

    River Publishers. 2017
  • “PReDiCt: A Scenario-based Methodology for Realizing Decision-Making Mechanisms Targeting Cyber-Physical Systems” in Book “Cyber-Physical Systems: Decision Making Mechanisms and Applications”

    River Publishers. 2017
  • “Supporting Decision Making for Large-Scale IoTs: Trading Accuracy with Computational Complexity”, in Book “Components and Services for IoT Platforms: Paving the Way for IoT Standards”

    Editors Nikolaos Voros, Georgios Keramidas and Michael Hübner, Springer, 2017
  • “Software Design and Optimization of ECG Signal Analysis and Diagnosis for Embedded IoT Devices,” in Book “Components and Services for IoT Platforms: Paving the Way for IoT Standards”

    Editors Nikolaos Voros, Georgios Keramidas and Michael Hübner, Springer. DOI 10.1007/978-3-319- 42304-3_15
  • “Architectures and CAD Tools for 3D FPGAs,” in Book “Reconfigurable Logic: Architecture, Tools and Applications,”

    CRC Press, 2015
  • “Efficient System Configurations for Dynamic Applications in Next Generation Mobile Communication Systems” Book Chapter in “Handbook of Research on Next Generation Mobile Communication Systems”

    IGI Global, A volume in the Advances in Wireless Technologies and Telecommunication (AWTT) Book Series
    • Cristina Silvano ,
    • William Fornaciari ,
    • S. Crespi Reghizzi ,
    • G. Agosta ,
    • G. Palermo ,
    • V. Zaccaria ,
    • Patrick Bellasi ,
    • F. Castro ,
    • Simone Corbetta ,
    • A. Di Biagio ,
    • E. Speziale ,
    • M. Tartara ,
    • D. Siorpaes ,
    • H. Hubert ,
    • B. Stabernack ,
    • J. Brandenburg ,
    • M. Palkovic ,
    • P. Raghavan ,
    • Chantal Ykman-Couvreur ,
    • Alexandros Bartzas ,
    • Sotirios Xydis ,
    • Dimitrios Soudris ,
    • T. Kempf ,
    • G. Ascheid ,
    • R. Leupers ,
    • H. Meyr ,
    • J. Ansari ,
    • P. Mahonen and
    • B. Vanthournout

    “2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures” Book Chapter in “VLSI 2010 Annual Symposium”

    Editors Lecture Notes in Electrical Engineering, Volume 57, pg. 65-79, 1st Edition., 2011, VIII, 331 p. Springer Netherlands, August 31, 2011, ISBN 978-94-007-1487-8
    • Christos Baloukas ,
    • Lazaros Papadopoulos ,
    • Dimitrios Soudris ,
    • S. Stuijk ,
    • O. Jovanovic ,
    • F. Schmoll ,
    • P. Marwedel ,
    • D. Cordes ,
    • R. Pyka ,
    • A. Mallik ,
    • Stylianos Mamagkakis ,
    • F. Capman ,
    • S. Collet ,
    • N. Mitas and
    • D. Kritharidis

    “Mapping embedded applications on MPSoCs: the MNEMEE approach” Book Chapter in “Designing Very Large Scale Integration Systems: Emerging Trends & Challenges”

    Editors: N. Voros, A. Mukherjee, N. Sklavos, K. Masselos, M. Huebner, Springer 2011
    • B. Candaele ,
    • S. Aguirre ,
    • M. Sarlotte ,
    • Iraklis Anagnostopoulos ,
    • Sotirios Xydis ,
    • Alexandros Bartzas ,
    • Dimitris Bekiaris ,
    • Dimitrios Soudris ,
    • Zhonghai Lu ,
    • Xiaowen Chen ,
    • J.M. Chabloz ,
    • A. Hemani ,
    • A. Jantsch ,
    • G. Vanmeerbeeck ,
    • J. Kreku ,
    • K. Tiensyrja ,
    • Fragkiskos Ieromnimon ,
    • D. Kritharidis ,
    • A. Wiefrink ,
    • B. Vanthournout and
    • P. Martin

    “The MOSART Mapping Optimization for multi-core ArchiTectures,” Book Chapter in “Designing Very Large Scale Integration Systems: Emerging Trends & Challenges”

    Editors: N. Voros, A. Mukherjee, N. Sklavos, K. Masselos, M. Huebner, Springer 2011
  • “A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning,” Book Chapter in “Designing Very Large Scale Integration Systems: Emerging Trends & Challenges”

    Editors: N. Voros, A. Mukherjee, N. Sklavos, K. Masselos, M. Huebner, Springer 2011
  • “A Temperature-Aware Placement and Routing Algorithm Targeting 3D FPGAs”, Book Chapter in “VLSI-SOC: Design Methodologies for SoC and SiP,”

    Piguet, R. Reis, and D. Soudris (Eds.): VLSI-SoC 2008, IFIP AICT 313, pp. 251–270, Springer, Dordrecht/London/Boston, Feb. 2010
  • Fast Instruction Memory Hierarchy Power Exploration for Embedded Systems,” Book Chapter in “VLSI-SOC: Design Methodologies for SoC and SiP”

    C. Piguet, R. Reis, and D. Soudris (Eds.): VLSI-SoC 2008, IFIP AICT 313, pp. 211–231, Springer
    • Christos Baloukas ,
    • Marijn Temmerman ,
    • Anne Keller ,
    • Stylianos Mamagkakis ,
    • Francky Catthoor ,
    • Dimitrios Soudris and
    • Serge Demeyer

    “Abstract and Concrete Data Type Optimizations at the UML and C/C++ Level for Dynamic Embedded Software,” in Book “Behavioral Modeling for Embedded Systems and Technologies: Applications for Design and Implementation”

    IGI-Global, ISBN: 978-1-60566-750- 8; 494, 2010
  • “Three Dimensional Network-on-Chip Architectures,” Chapter 2, in “Networks-on-Chips: Theory and practice”

    CRC Press, 2008
    • Dimitrios Soudris ,
    • Konstantinos Tatas ,
    • Kostas Siozios ,
    • G. Koutroumpezis ,
    • Spyridon Nikolaidis ,
    • Stylianos Siskos ,
    • N. Vasiliadis ,
    • V. Kalenteridis ,
    • H. Pournara and
    • I. Pappas

    “AMDREL: A Novel Low-Energy FPGA Architecture and Supporting CAD Tool Design Flow”, Chapter 3 in “Fine and Coarse-Grain Reconfigurable Systems”

    Editors: S. Vassiliadis and D. Soudris, Springer, 2007
  • Survey of Coarse-Grain Reconfigurable Architectures and Processors,” Chapter 2 in “Fine and Coarse-Grain Reconfigurable Systems”

    Editors: S. Vassiliadis and D. Soudris, Springer, 2007
  • “Survey of Fine-Grain Reconfigurable Architectures and Processors”, Chapter 1 in “Fine- and Coarse-Grain Reconfigurable Systems”

    Editors: S. Vassiliadis and D. Soudris, Springer, 2007
  • “CHAPTER 10. Circuit techniques for dynamic power reduction” in “Low- Power Electronics Design”

    Editor C. Piguet, CRC Press Book, 2005
  • “Logic level Power Optimization,” in “Designing CMOS Circuits for Low Power”

    Kluwer Academic Publishers
  • “Sources of Power Dissipation in CMOS Circuits” in “Designing CMOS Circuits for Low Power”

    Kluwer Academic Publishers
  • “Power Management for Digital Receivers,” in “Unified Low-Power Design Flow for Data-Dominated multimedia and telecom applications”

    Editor F. Catthoor, Kluwer Academic Publishers

    Journals

  • Bringing Energy Efficiency closer to Application Developers: An Extensible Software Analysis Framework

    IEEE Transactions on Sustainable Computing
      BibTeX
  • Translating quality-driven code change selection to an instance of multiple-criteria decision making

    Elsevier Information and Software Technology
      BibTeX
  • Decision support for GPU acceleration by predicting energy savings and programming effort

    Elsevier Sustainable Computing: Informatics and Systems
      BibTeX
  • A flexible tool for estimating applications performance and energy consumption through static analysis

    SN Computer Science
      BibTeX
  • Hardware Approximate Techniques for Deep Neural Network Accelerators: A Survey

    ACM Computing Surveys (CSUR)
  • Design Space Exploration on High-Order QAM Demodulation Circuits: Algorithms, Arithmetic and Approximation Techniques

    Electronics
  • Multinode implementation of an extended Hodgkin–Huxley simulator

    Neurocomputing, 2019, DOI: 10.1016/j.neucom.2018.10.062
  • Runtime slack creation for processor performance variability using system scenarios

    ACM Transactions on Design Automation of Electronic Systems DOI: 10.1145/3152158
  • Distributed Trade-Based Edge Device Management in Multi-Gateway IoT

    ACM Transactions on Cyber-Physical Systems DOI: 10.1145/3134842
  • Walking through the Energy-Error Pareto Frontier of Approximate Multipliers

    IEEE Micro DOI: 10.1109/MM.2018.043191124
  • OpenCL-based virtual prototyping and simulation of many-accelerator architectures

    ACM Transactions on Embedded Computing Systems DOI: 10.1145/3242179
  • A novel framework for the seamless integration of FPGA accelerators with big data analytics frameworks in heterogeneous data centers

    Proceedings - 2018 International Conference on High Performance Computing and Simulation, HPCS 2018 DOI: 10.1109/HPCS.2018.00090
  • A design space exploration framework for convolutional neural networks implemented on edge devices

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems DOI: 10.1109/TCAD.2018.2857280
  • TID evaluation system with on-chip electron source and programmable sensing mechanisms on FPGA

    IEEE Transactions on Nuclear Science, 2019, DOI: 10.1109/TNS.2018.2885713
  • Rusty: Runtime Interference-Aware Predictive Monitoring for Modern Multi-Tenant Systems

    IEEE Transactions on Parallel and Distributed Systems, 2021, DOI: 10.1109/TPDS.2020.3013948
  • Approximate similarity search with FAISS framework using FPGAs on the cloud

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2019, DOI: 10.1007/978-3-030-27562-4_27
  • A cost-benefit analysis for reconfigurable PV modules under shading

    Solar Energy, 2019, DOI: 10.1016/j.solener.2018.11.063
  • Multinode implementation of an extended Hodgkin-Huxley simulator

    Neurocomputing, 2019
  • Single- and multi-FPGA acceleration of dense stereo vision for planetary rovers

    ACM Transactions on Embedded Computing Systems, 2019, DOI: 10.1145/3312743
  • Oops: Optimizing operation-mode selection for IoT edge devices

    ACM Transactions on Internet Technology, 2019, DOI: 10.1145/3230642
  • Multi-Level Approximate Accelerator Synthesis under Voltage Island Constraints

    IEEE Transactions on Circuits and Systems II: Express Briefs, 2019, DOI: 10.1109/TCSII.2018.2869025
  • In-the-Field Mitigation of Process Variability for Improved FPGA Performance

    IEEE Transactions on Computers, 2019, DOI: 10.1109/TC.2019.2898833
  • Rusty: Runtime System Predictability Leveraging LSTM Neural Networks

    IEEE Computer Architecture Letters, 2019, DOI: 10.1109/LCA.2019.2924622
  • LOOG: Improving GPU Efficiency with Light-Weight Out-Of-Order Execution

    IEEE Computer Architecture Letters, 2019, DOI: 10.1109/LCA.2019.2951161
  • Energy-efficient VLSI implementation of multipliers with double LSB operands

    IET Circuits, Devices and Systems, 2019, DOI: 10.1049/iet-cds.2018.5039
  • A closed-loop controller to ensure performance and temperature constraints for dynamic applications

    ACM Transactions on Embedded Computing Systems, 2019, DOI: 10.1145/3343030
  • Fast Operation Mode Selection for Highly Efficient IoT Edge Devices

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020, DOI: 10.1109/TCAD.2019.2897633
  • High-Performance Vision-Based Navigation on SoC FPGA for Spacecraft Proximity Operations

    IEEE Transactions on Circuits and Systems for Video Technology, 2020, DOI: 10.1109/TCSVT.2019.2900802
  • Analog fiber-wireless downlink transmission of IFoF/mmWave over in-field deployed legacy PON infrastructure for 5G fronthauling

    Journal of Optical Communications and Networking, 2020, DOI: 10.1364/JOCN.391803
  • Rapid Prototyping of Low-Complexity Orchestrator Targeting CyberPhysical Systems: The Smart-Thermostat Usecase

    IEEE Transactions on Control Systems Technology
      BibTeX
  • A Message-Passing Microcoded Synchronization for Distributed Shared Memory Architectures

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), DOI: 10.1109/TCAD.2018.2834423
  • A Method for Detailed, Short-Term Energy Yield Forecasting of Photovoltaic Installations

    Renewable Energy, Elsevier
  • Decoupled MapReduce for SharedMemory Multi-core Architectures

    IEEE Computer Architecture Letters. July-December 2018 DOI: 10.1109/LCA.2018.2827929
  • Failure probability of a FinFET-based SRAM cell utilizing the most probable failure point

    Integration, Elsevier, March 2018 DOI: 10.1109/PATMOS.2017.8106967
  • CF-TUNE: Collaborative Filtering Auto-Tuning for Energy Efficient Many-Core Processors

    IEEE Computer Architecture Letters (Volume: 17, Issue: 1, Jan.-June 1 2018) DOI: 10.1109/LCA.2017.2716919
  • High-Performance Embedded Computing in Space: Evaluation of Platforms for Vision-Based Navigation

    Journal of Aerospace Information Systems, Feb. 2018 DOI: 10.2514/1.I010555
  • VOSsim: A Framework for Enabling Fast Voltage Over-Scaling Simulation for Approximate Computing Circuits

    IEEE Transactions on Very Large Scale Integration Systems, Volume: 26, Issue: 6, June 2018 DOI: 10.1109/TVLSI.2018.2803202
  • Hierarchical Distributed Run-time Resource Management scheme for NoC based Many-Cores

    ACM Trans. On Embedded Computing Systems (TECS) Vol. 17, No. 3, Article 65. Publication date: April 2018
  • Application-Arrival Rate Aware Distributed Run-Time Resource Management for Many-core Computing Platforms

    IEEE Transactions on Multi-Scale Computing Systems 2018 DOI: 10.1109/TMSCS.2018.2793189
  • Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers

    IEEE Transactions On Very Large Scale Integration (VLSI) Systems, 26 (3), 2018 DOI: 10.1109/TVLSI.2017.2767858
  • Run Time Slack Creation for Processor Performance Variability using System Scenarios Consistent

    ACM Trans. on Design Automation of Electronic Systems(TODAES), Vol. 23, No. 2, Article 24, December 2017
  • BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations

    Journal of Neural Engineering, Vol. 14, No. 6, 2017 DOI: 10.1088/1741-2552/aa7fc5
  • Systematic cross-validation of photovoltaic energy yield models for dynamic environmental conditions

    Solar Energy, Volume 155, October 2017
  • SoftRM: SelfOrganized Fault-Tolerant Resource Management for Failure Detection and Recovery in NoC based Many-Cores

    ACM Transactions on Embedded Computing Systems (TECS), special issue of paper from CODES+ISSS: International Conference on Hardware/Software Codesign, and System Synthesis, Seoul, South Korea October 15-20, 2017 DOI: 10.1145/3126562
  • A Flexible Decision-Making Mechanism Targeting Smart Thermostats

    IEEE Embedded Systems Letters, 9 (4), 2017 DOI: 10.1109/LES.2017.2748235
  • On Supporting Rapid Prototyping of Embedded Systems with Reconfigurable Architectures

    Integration, the VLSI Journal, 58 (2017)
  • An Exploration Framework for Efficient High-Level Synthesis of Support Vector Machines: Case Study on ECG Arrhythmia Detection for Xilinx Zynq SoC

    Journal of Signal Processing Systems, March 2017 DOI: 10.1007/s11265-017-1230-1
  • Optimizing Extended Hodgkin-Huxley Neuron Model Simulations for a Xeon/Xeon Phi Node

    IEEE Trans. On Parallel and Distributed Computing, Sept. 2017 DOI: 10.1109/TPDS.2017.2686389
  • A Low-Complexity Control Mechanism Targeting Smart Thermostats

    Energy and Buildings, Elsevier, 139 (2017)
  • A Flexible, High-Performance FPGA Implementation of a Feed-Forward Equalizer for Optical Interconnects up to 112 Gb/s

    Journal of Signal Processing Systems, 26 November 2016 DOI: 10.1007/s11265-016-1201-y
  • An FPGA-based Integrated MapReduce Accelerator Platform

    Journal of Signal Processing Systems 2017
  • DesignEfficient Approximate Multiplication Circuits Through Partial Product Perforation

    IEEE Transactions on Very Large Scale Integration Systems (VLSI), 2016
  • A Framework for Interconnection-Aware Domain-Specific Many-Accelerator Synthesis

    ACM Transactions on Embedded Computing Systems (TECS), Volume 16 Issue 1, November 2016
  • Customization Methodology for Implementation of Streaming Aggregation in Embedded Systems

    Journal of Systems Architecture, Volumes 66–67, May 2016
  • Efficient variability analysis of arithmetic units using linear regression techniques

    Analog Integrated Circuits and Signal Processing, Springer, (2016)
  • ANT3D: Simultaneous Partitioning and Placement for 3-D FPGAs based on Ant Colony Optimization

    IEEE Embedded Systems Letters, 2016
  • A Customizable Framework for Application Implementation onto 3-D FPGAs

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.: 35, Issue: 11, Nov. 2016
  • An Integrated Exploration and Virtual Platform Framework for Many-Accelerator Heterogeneous Systems

    ACM Transactions on Embedded Computing Systems (TECS), Volume 15 Issue 3, July 2016
  • Near-Static Shading Exploration for Smart Photovoltaic Module Topologies Based on Snake-like Configurations

    ACM Transactions on Embedded Computing Systems (TECS), 15(2): 27:1-27:21, (2016)
  • Concurrent Data Structure Optimization Methodology for Embedded Systems

    IEEE Transactions on Computers. Volume: 65, Issue: 7, July 1 2016
  • HW/SW co-design and FPGA acceleration of visual odometry algorithms for rover navigation on Mars

    IEEE Transactions on Circuits and Systems for Video Technology, Volume: 26, Issue: 8, Aug. 2016
  • A Survey on FEC Codes for 100G and Beyond Optical Networks

    IEEE Communications: Surveys and Tutorials, 27 January 2016
  • An Evolutionary Algorithm for Netlist Partitioning Targeting 3-D FPGAs

    IEEE Embedded Systems Letters, Volume:7, Issue: 4, December 2015
  • A MapReduce Scratchpad Memory for Multi–core Cloud Computing Applications

    Microprocessors and Microsystems (MICPRO), 39 (2015)
  • Mitigating Memoryinduced Dark Silicon in Many-Accelerator Architectures

    IEEE Computer Architecture Letters, Vol.: 14, Issue: 2, March 2015
    • Dimitris Rodopoulos ,
    • Georgia Psychou ,
    • Mohamed M. Sabry ,
    • Francky Catthoor ,
    • Antonis Papanikolaou ,
    • Dimitrios Soudris ,
    • Tobias G. Noll and
    • D. Atienza

    Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations

    Journal of ACM Computing Surveys,Volume 47 Issue 3, April 2015
  • Hybrid (HWSW) Mitigation of Transient Errors on the Data Plane of the Single-Chip Cloud Computer

    IEEE Transactions on Very Large Scale Integration (VLSI), Vol.: 23, Issue: 3, March 2015
  • GENESIS: Parallel Application Placement onto Reconfigurable Architectures

    ACM TECS, Trans. Embedded Computing Systems, Vol. 14, No. 1, Article 18, January 2015
    • Miguel Peon ,
    • Alexandros Bartzas ,
    • Stylianos Mamagkakis ,
    • Francky Catthoor ,
    • J. Mendias and
    • Dimitrios Soudris

    Placement of Linked Dynamic Data Structures over Heterogeneous Memories in Embedded Systems

    ACM TECS, ACM Transactions on Embedded Computing Systems, Volume 14 Issue 2, March 2015
  • Tackling Performance Variability due to RAS Mechanisms with PID-Controlled DVFS

    IEEE Computer Architecture Letters. (Volume:PP, Issue: 99), 23 December 2014
  • Plug&Chip: A Framework for Supporting Rapid Prototyping of 3-D Hybrid Virtual SoCs

    ACM Transactions on Embedded Computing Systems (TECS), Vol. 13, No. 5s, Article 168, November 2014
  • Atomistic Pseudo-Transient BTI Simulation with Inherent Workload Memory

    IEEE Transactions On Device And Materials Reliability, vol. 14, no. 2, June 2014
  • A Framework for Supporting Adaptive Fault Tolerant Solutions

    ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Risk and Trust in Embedded Critical Systems, Special Issue on Real-Time, Embedded and CyberPhysical Systems, Special Issue on Virtual Prototyping of Parallel and Embedded Systems (ViPES), Volume 13 Issue 5s, November 2014
  • A Novel 3-D FPGA Architecture Targeting Communication Intensive Applications

    Journal of Systems Architecture, Volume 60, Issue 1,January 2014
  • SPARTAN: Developing a Vision System for Future Autonomous Space Exploration Robots

    Journal of Field Robotics, Special Issue: Special Issue on Space Robotics, Part 2, Volume 31, Issue 1, pages 107– 140, January/February 2014
  • A low-cost fault tolerant solution targeting commercial FPGA devices

    Journal of Systems Architecture, 59 (2013)
  • A Framework for Rapid Evaluation of Heterogeneous 3-D NoC Architectures

    Microprocessors and Microsystems, Elsevier. October 2013
  • System Scenarios-based Architecture Level Exploration of SDR Application using a Network-on-Chip Simulation Framework

    MICRO: Microprocessors and Microsystems, 2013, Elsevier, Volume 37, Issues 6–7, August–October 2013
  • JITPR: A Framework for Supporting Fast Application’s Implementation onto FPGAs (RAW 2012 special issue)

    ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012), Volume 6, Issue 2, July 2013
  • Power-aware Dynamic Memory Management on Many-core Platforms utilizing DVFS

    ACM TECS, ACM Transactions on Embedded Computing Systems, Vol. 13, No. 1s, Article 40, November 2013
  • On Supporting Rapid Exploration of Memory Hierarchies onto FPGAs

    Journal of Systems Architecture, Journal of Systems Architecture 59 (2013)
  • High-level customization framework for application-specific NoC architectures

    Design Automation for Embedded Systems, Springer Publishers, November 2012
  • Enabling Efficient System Configurations For Dynamic Wireless Applications Using System Scenarios

    International Journal of Wireless Information Networks, Springer Publishers, 2012
  • A Framework for Performing Rapid Evaluation of 3-D SoCs

    Electronics Letters, Volume: 48, Issue: 12, pp. 679 – 681, 7 June 2012
  • A Systematic Methodology for Reliability Improvements on SoC-based Software Defined Radio Systems

    VLSI Design, Volume 2012
  • Compiler-in-the-Loop Exploration During Datapath Synthesis for Higher Quality Delay-Area Trade-offs

    ACM TODAES, Transactions on Design Automation of Electronic Systems, Vol. 18, No. 1, Article 11, December 2012
  • A Novel Framework for Exploring 3-D FPGAs with Heterogeneous Interconnect Fabric

    in ACM Transactions on Reconfigurable Technology and Systems, Vol. 5, Issue 1, March 2012
  • A Tabu-based Partitioning Algorithm Targeting to 3-D FPGAs

    IEEE Embedded Systems Letters, Vol. 3, No. 3, September 2011
  • On Supporting Rapid Thermal Analysis

    IEEE Computer Architecture Letters, Issue Date: July-Dec. 2011
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    IEEE Embedded Systems Letters. Volume: 3 Issue:2, June 2011
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    Microprocessors and Microsystems, Elsevier Publishers, 35 (2011)
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    IEEE Transactions on VLSI Systems, 19, No. 3, March 2011
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    Software Metadata: Systematic Characterization of the Memory Behaviour of Dynamic Applications

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  • A Novel Allocation Methodology for Partial and Dynamic Bitstream Generation of FPGA Architectures

    Journal of Circuits, Systems, and Computers, JCSC, Vol. 19, No. 3 (2010)
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    International Journal of Communication Systems, Wiley & Sons. 2009
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    IET-Computers & Digital Techniques, Vol. 3, Issue: 2, 2009
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  • Optimization Methodology of Dynamic Data Structures based on Genetic Algorithms for Multimedia Embedded Systems

    Journal of Systems and Software 82 (2009)
  • A System-Level Design Methodology for ApplicationSpecific Networks-on-Chip

    Journal of Embedded Computing, IOS press, Volume 3, Number 3, July 2009
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    • Dimitrios Soudris

    Direct Memory Access Usage Optimization in Network Applications for Reduced Memory Latency and Energy Consumption

    Journal of Embedded Computing, IOS press, Volume 3, Number 3, July 2009
  • A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs

    JOLPE - Journal of Low Power Electronics, Vol. 4, Νο. 3, pp. 275–289, 2008
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    International Journal of Reconfigurable Computing, Volume 2008 (2008)
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    JOLPE - Journal of Low Power Electronics, 4, 34-47 (2008)
  • Optimal Data Structure Exploration for Multimedia and Network Applications in Embedded Systems

    Journal of Systems Architecture, Volume 54, Issue 11, (November 2008)
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    IEEE Transactions on Circuits and Systems I: Regular papers, vol. 55, no. 2, March 2008
  • Systematic methodology for designing low power direct digital frequency synthesisers

    IET Proceedings – Circuits, Devices and Systems, Vol. 1, No. 4, August 2007
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    • Adonios Thanailakis

    Systematic Methodology for Exploration of Performance – Energy Trade-offs in Network Applications Using Dynamic Data Type Refinement

    Journal of Systems Architecture 53 (2007)
  • Automated Framework for Partitioning DSP Applications in Hybrid Reconfigurable Platforms

    Microprocessors and Microsystems, 31(1), 1-14, 2007
  • Architecture Design of a Coarse-Grain Reconfigurable Multiply-accumulate unit for Data Intensive Applications

    Integration, The VLSI Journal, Volume 40, Issue 2 , February 2007
  • Power Management through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers

    JOLPE - Journal of Low Power Electronics, Volume 2, Number 3, December 2006
  • A Method for Partitioning Applications in Hybrid Reconfigurable Architectures

    Design Automation for Embedded Systems, vol. 10 (1), pp. 27-47, March 2006
    • Stylianos Mamagkakis ,
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    Reducing Memory Fragmentation with Performance-optimized Dynamic Memory Allocators in Network Applications

    Computer Communications, 29 (2006)
    • Minas Dasigenis ,
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    A Combined DMA and Application Specific Prefetching Approach for Tackling the Memory Latency Bottleneck

    IEEE Transactions on VLSI Systems, Vol. 14, No. 3, March 2006
    • Nikolaos Kroupis ,
    • Nikos Zervas ,
    • Minas Dasigenis ,
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    • Dimitrios Soudris and
    • Adonios Thanailakis

    Power, Performance and Area Exploration of Block Matching Algorithms Mapped on Programmable Processors

    Journal of VLSI Signal Processing, 44 (1-2): 153-171 AUG 2006
  • Systematic Dynamic Memory Management Design Methodology for Reduced Memory Footprint

    ACM Transactions on Design Automation of Electronic Systems (TODAES) Vol. 11, No. 2, April 2006
    • D. Atienza ,
    • Stylianos Mamagkakis ,
    • F. Poletti ,
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    • Francky Catthoor ,
    • L. Benini and
    • Dimitrios Soudris

    Efficient System-Level Prototyping of Power-Aware Dynamic Memory Managers for Embedded Systems

    Integration, The VLSI Journal, Volume 39, Issue 2, March 2006
    • Kostas Siozios ,
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    • Konstantinos Tatas ,
    • N. Vasiliadis ,
    • V. Kalenteridis ,
    • H. Pournara ,
    • I. Pappas ,
    • Dimitrios Soudris ,
    • Adonios Thanailakis ,
    • Spyridon Nikolaidis and
    • Stylianos Siskos

    A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications

    IEICE Transactions on Information and Systems, "Special Issue on Recent Advances in Circuits and Systems", vol. E88-D, No. 7 July 2005
  • Behavioral-Level Event-Driven Power Management for DECT Digital Receivers

    Microelectronics Journal, 36 (2): 163-172 FEB 2005
    • V. Kalenteridis ,
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    • I. Pappas ,
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    • Spyridon Nikolaidis ,
    • Stylianos Siskos ,
    • Dimitrios Soudris and
    • Adonios Thanailakis

    A Complete Platform and Toolset for System Implementation on Fine-Grain Reconfigurable Hardware

    Microprocessors and Microsystems, Special Issue on Field-Programmable Gate Arrays (FPGAs): Applications, Algorithms and Tools, Elsevier Publishers, 29 (2005)
  • Novel Division Algorithm and Architectures for Parallel and Sequential Processing

    Journal of Circuits, Systems, and Computers, Vol. 14, No. 2, April 2005
  • Memory Power Optimization Of Hardware Implementations Of Multimedia Applications Onto FPGA Platforms

    Journal of Embedded Computing, Cambridge International Science Publishing, Volume 1, Number 3 / 2005
  • The Low Power Analogue and Digital Baseband Processing Parts of a Novel Multimode DECT/GSM/DCS1800 Terminal

    Microelectronics Journal, 35 (2004)
  • A Color Quantization Technique Based On Image Decomposition and Its Embedded System Implementation

    IEEProceedings Vision, Image and Signal Processing, Vol. 151, Issue 6, 2004
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    IEICE Trans. On Electronics, E87C (6): 1054-1061 June 2004
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    • Minas Dasigenis ,
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    • Adonios Thanailakis

    Data Memory Power Optimization and Performance Exploration of Embedded Systems for Implementing Motion Estimation Algorithms

    Real-Time Imaging Volume 9, Issue 6 , December 2003
  • ALow Power baseband processor for a portable dual mode DECT/GSM terminal

    IEICE Trans. On Information & Systems: Special Section/Issue on "Development of Advanced Computer Systems, E86D (10): 1976-1986 OCT 2003
    • Minas Dasigenis ,
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    Power and performance exploration of embedded systems executing multimedia kernels

    IEE ProceedingsComputer and Digital Techniques, Vol. 149, No.4, July 2002
  • RNS and QRNS Full-Adder Based Converters

    IEE Proceedings-Circuits, Devices, and Systems, Vol. 149, No. 4, August 2002
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    • Adonios Thanailakis

    A fast and accurate delay dependent method for switching activity estimation of large combinational circuits

    Journal of System Architecture, Volume 48, Issue 4-5, December 2002
    • Nikos Zervas ,
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    • Dimitrios Soudris ,
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    • Costas Goutis

    Low-Power Design of a Digital Baseband Receiver for Direct Conversion DECT Systems

    IEEE Transactions on Circuits and Systems-Part-II: Analog and Digital Signal Processing, vol. 48, no. 12, December 2001
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    VLSI Design, Journal of Custom-Chip Design, Simulation, and Testing, Vol. 12, No. 2, 2001
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    VLSI Design, Journal of Custom-Chip Design, Simulation, and Testing, vol. 12, no. 1, 2001
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    IEE Proceedings-Computer and Digital Techniques, vol. 147, no. 6, Nov. 2000
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    A new simulator for the oxidation process in integrated circuits fabrication based on cellular automata

    Modelling and Simulation in Materials Science and Engineering, 7, 1999
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    VLSI Design, Journal of Custom-Chip Design, Simulation, and Testing, Special Issue: High-performance Bus-Based Architectures, Vol. 9. No. 2, 1999
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    IEE Proceedings-Computer and Digital Techniques, September 1998
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    Design Methodology for systematic derivation of fault-tolerant processor array architectures

    International Journal of Electronics, vol. 84, no. 6, 1998
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    Quaternary voltage-mode CMOS circuits for Multiple-Valued Logic

    IEE Proceedings-Circuits, Devices, and Systems, vol. 145, April 1998
  • Neural Networks for the Simulation of Photoresist Exposure Process in Integrated Circuit Fabrication

    Modelling and Simulation in Materials Science and Engineering, 5, 1997
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    IEE Proceedings-Circuits, Devices, and Systems, vol. 144, December 1997
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    IEEE Transactions on Circuits and Systems II, Vol. 44, No. 4, April 1997
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    Journal of Circuits, Systems, and Computers, Vol. 6, No.3, 1996
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    Inter. Journal of Electronics, vol. 79, no. 5, 1995
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    On The Design of Two-Level Pipelined Processor Arrays

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    Conferences

  • Thermal Comfort Aware Online Energy Management Framework for a Smart Residential Building

    2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)
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  • SDK4ED: One-click platform for Energy-aware, Maintainable and Dependable Applications

    2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)
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    2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)
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  • Cross-layer approximation for printed machine learning circuits

    2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 190-195
  • ApproxQAM: High-Order QAM Demodulation Circuits with Approximate Arithmetic

    2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)
  • A Framework Exploiting Process Variability to Improve Energy Efficiency in FPGA Applications

    GLSVLSI '18: Proceedings of the 2018 on Great Lakes Symposium on VLSI, DOI: https://doi.org/10.1145/3194554.3194569
  • Memory Footprint Optimization Techniques for Machine Learning Applications in Embedded Systems

    2020 IEEE International Symposium on Circuits and Systems (ISCAS), DOI: https://doi.org/10.1109/ISCAS45731.2020.9181038
  • FPGA acceleration of hyperspectral image processing for high-speed detection applications

    Proceedings - IEEE International Symposium on Circuits and Systems DOI: 10.1109/ISCAS.2017.8050773
  • VineTalk: Simplifying software access and sharing of FPGAs in datacenters

    2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017 DOI: 10.23919/FPL.2017.8056788
  • FPGA acceleration of spark applications in a Pynq cluster

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  • From edge to cloud: Design and implementation of a healthcare internet of things infrastructure

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    Proceedings - 2017 17th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2017 DOI: 10.1109/SAMOS.2017.8344641
  • Carrier Phase Recovery of 64 GBd Optical 16-QAM Using Extensive Parallelization on an FPGA

    Proceedings - IEEE International Symposium on Circuits and Systems DOI: 10.1109/ISCAS.2018.8351581
  • Interrelations between software quality metrics, performance and energy consumption in embedded applications

    Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems, SCOPES 2018 DOI: 10.1145/3207719.3207736
  • A framework exploiting process variability to improve energy eficiency in FPGA applications

    Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI DOI: 10.1145/3194554.3194569
  • Efficient support vector machines implementation on Intel/Movidius Myriad 2

    2018 7th International Conference on Modern Circuits and Systems Technologies, MOCAST 2018 DOI: 10.1109/MOCAST.2018.8376630
  • Acceleration of image classification with Caffe framework using FPGA

    2018 7th International Conference on Modern Circuits and Systems Technologies, MOCAST 2018 DOI: 10.1109/MOCAST.2018.8376580
  • Real-time carrier phase recovery for 16-QAM utilizing the nonlinear least squares algorithm

    2018 Optical Fiber Communications Conference and Exposition, OFC 2018 - Proceedings DOI: 10.1364/OFC.2018.W2A.49
  • Efficient winograd-based convolution kernel implementation on edge devices

    Proceedings - Design Automation Conference DOI: 10.1145/3195970.3196041
  • EXA2PRO programming environment: Architecture and applications

    ACM International Conference Proceeding Series DOI: 10.1145/3229631.3239369
  • The VINEYARD integrated framework for hardware accelerators in the cloud

    ACM International Conference Proceeding Series DOI: 10.1145/3229631.3236093
  • BLonD++: Performance analysis and optimizations for enabling complex, accurate and fast beam dynamics studies

    ACM International Conference Proceeding Series DOI: 10.1145/3229631.3229640
    • Michail Noltsis ,
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    • Chrysostomos Nicopoulos ,
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    • Davide Zoni and
    • Dimitrios Soudris

    Fast estimations of failure probability over long time spans

    Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018 DOI: 10.1145/3232195.3232198
  • Evaluation Methodology and Reconfiguration Tests on the New European NG-MEDIUM FPGA

    2018 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2018, DOI: 10.1109/AHS.2018.8541492
    • P. Manganiello ,
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    Optimization Methodology for Reconfigurable PV Modules

    2018 IEEE 7th World Conference on Photovoltaic Energy Conversion, WCPEC 2018 - A Joint Conference of 45th IEEE PVSC, 28th PVSEC and 34th EU PVSEC, DOI: 10.1109/PVSC.2018.8548246
  • The VINEYARD Framework for Heterogeneous Cloud Applications: The BrainFrame Case

    Conference on Design and Architectures for Signal and Image Processing, DASIP, 2018, DOI: 10.1109/DASIP.2018.8597119
  • Hardware acceleration of image registration algorithm on FPGA-based systems on chip

    ACM International Conference Proceeding Series, 2019, DOI: 10.1145/3312614.3312636
  • Parity Based In-Place FFT Architecture for Continuous Flow Applications

    2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018, DOI: 10.1109/ICECS.2018.8617990
  • Parallel Robust Absolute Orientation on FPGA for Vision and Robotics

    2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018, DOI: 10.1109/ICECS.2018.8617856
  • Design and Performance Comparison of CNN Accelerators Based on the Intel Movidius Myriad2 SoC and FPGA Embedded Prototype

    Proceedings - 2019 3rd International Conference on Control, Artificial Intelligence, Robotics and Optimization, ICCAIRO 2019, DOI: 10.1109/ICCAIRO47923.2019.00030
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    2019 8th International Conference on Modern Circuits and Systems Technologies, MOCAST 2019, DOI: 10.1109/MOCAST.2019.8741940
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    2019 8th International Conference on Modern Circuits and Systems Technologies, MOCAST 2019, DOI: 10.1109/MOCAST.2019.8741875
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    Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019, DOI: 10.23919/DATE.2019.8714934
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    Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019, DOI: 10.23919/DATE.2019.8715018
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    Proceedings - Design Automation Conference, 2019, DOI: 10.1145/3316781.3317793
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    2019 IEEE 29th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2019, DOI: 10.1109/PATMOS.2019.8862032
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    Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019, DOI: 10.1109/FPL.2019.00021
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    Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019, DOI: 10.1109/FPL.2019.00016
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    Proceedings - 2019 IEEE 19th International Conference on Bioinformatics and Bioengineering, BIBE 2019, DOI: 10.1109/BIBE.2019.00067
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    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2020, DOI: 10.1007/978-3-030-38085-4_46
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    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2020, DOI: 10.1007/978-3-030-58811-3_73
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    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2020, DOI: 10.1007/978-3-030-60939-9_25
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    Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020, DOI: 10.23919/DATE48585.2020.9116281
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    Proceedings - 28th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2020, DOI: 10.1109/FCCM48280.2020.00070
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    17th ACM International Conference on Computing Frontiers 2020, CF 2020 - Proceedings, DOI: 10.1145/3387902.3392616
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    IEEE/ASME International Conference on Advanced Intelligent Mechatronics, AIM, 2020, DOI: 10.1109/AIM43001.2020.9159012
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    Proceedings - Design Automation Conference, 2020, DOI: 10.1109/DAC18072.2020.9218734
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    2020 9th International Conference on Modern Circuits and Systems Technologies, MOCAST 2020, DOI: 10.1109/MOCAST49295.2020.9200255
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    Proceedings - IEEE 20th International Conference on Bioinformatics and Bioengineering, BIBE 2020, DOI: 10.1109/BIBE50027.2020.00071
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    ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings, DOI: 10.1109/ICECS49266.2020.9294869
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    in Proceedings of International Workshop on Software and Compilers for Embedded Systems (SCOPES) 2020
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    in Proceedings of EU PVSEC European PV Solar Energy Conference amd Exhibition, 2019
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    in IXPUG Workshop, Co-located with ISC, 2017
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    in IEEE International Geoscience and Remote Sensing Symposium, 2017 DOI: 10.1109/IGARSS.2017.8126969
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    in Proc. of The International Conference on Modern Circuits and Systems Technologies (MOCAST), 2017
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    HARPA: Tackling Physically Induced Performance Variability

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    in Proc. 20th Design Automation & Testing Exhibition (DATE), 2017
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    in ACM Proc. of PCI, 2016
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    2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2016
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    in Proc. of 23rd IEEE International Conference on Electronics Circuits and Systems (ICECS), 2016
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    in IEEE World Forum on Internet of Things, 2016
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    in Workshop on Approximate Computing, 2016
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    in Proc. of International Conference on Field-Programmable Logic and Applications (FPL), 2016
  • Energy Profile Analysis of Zynq-7000 Programmable SoC for Embedded Medical Processing: Case study on ECG Arrhythmia Detection

    in Proc. of 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2016
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    in International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2016
  • Performance and Energy evaluation of Spark applications on low-power SoCs

    in Proc. of International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2016
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    in 4th Workshop on Virtual Prototyping of Parallel and Embedded Systems (VIPES), 2016
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    in 4th Workshop on Virtual Prototyping of Parallel and Embedded Systems, co-located with the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2016
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    in Proc. of 2016 International Conference on IC Design and Technology (ICICDT), 2016
  • ECG Signal Analysis and Arrhythmia Detection on IoT wearable medical devices

    in Proc. of 5th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2016
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    • Georgi Gaydajiev ,
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    • Angelos Bilas ,
    • Neil Morgan ,
    • Christos Strydis ,
    • Vasilis Spatadakis ,
    • Dimitris Gardelis ,
    • Ricardo Jimenez-Peris and
    • Alexandre Almeida

    The VINEYARD project: Versatile Integrated Accelerator-based Heterogeneous Data Centers

    in Proc. of 5th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2016
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    in Proc. of 5th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2016
  • Proposed Evaluation Framework for Exploration of Smart PV Module Topologies

    in Proceedings of EU PVSEC European PV Solar Energy Conference and Exhibition, 2016
  • Evaluation of a Detailed Electro-Thermal PV Model on a 62.5 KWp Installation

    in Proceedings of EU PVSEC European PV Solar Energy Conference amd Exhibition, 2016
  • First Impressions from Detailed Brain Model Simulations on a Xeon-Xeon Phi Node

    in Proc. of ACM International Conference on Computing Frontiers (CF), 2016
  • Performance Analysis of Accelerated Biophysically-Meaningful Neuron Simulations

    in Proc. of ISPASS: IEEE Int. Symposium on Performance Analysis of Systems and Software, 2016
  • Deploying and Monitoring Hadoop MapReduce Analytics on Single-chip Cloud Computer

    PARMA-DITAM Workshop, 7th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures – 5th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2016
    • Dimitrios Stamoulis ,
    • Simone Corbetta ,
    • Dimitris Rodopoulos ,
    • Pieter Weckx ,
    • Peter Debacker ,
    • Brett H. Meyer ,
    • Ben Kaczer ,
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    • Francky Catthoor and
    • Zeljko Zilic

    Capturing true workload dependency of BTI-induced degradation in CPU components

    in Proc. of 6th GLSVLSI: Great Lakes Symposium, 2016
    • Christoforos Kachris ,
    • Dimitrios Soudris ,
    • Georgi Gaydajiev ,
    • Huy-Nam Nguyen ,
    • Dimitrios Nikopoulos ,
    • Angelos Bilas ,
    • Neil Morgan ,
    • Christos Strydis ,
    • Christos Tsalidis ,
    • John Balafas ,
    • Ricardo Jimenez-Peris and
    • Alexandre Almeida

    The VINEYARD approach: Versatile, Integrated, Accelerator based, Heterogeneous Data Centers

    in Applied Reconfigurable Computing (ARC), 2016
  • Many-core CPUs can deliver scalable performance to stochastic simulations of large-scale biochemical reaction networks

    in proceedings of International Conference on High Performance Computing & Simulation (HPCS), 2015
  • Advancing Integrated and Personalized Healthcare Services, the AEGLE Approach

    in Special Project Session on Cyber-Physical Systems, in the 18th IEEE International Conference on Computational Science and Engineering (CSE), 2015
  • High-Level Synthesis Extensions for Scalable Single-Chip Many-Accelerators on FPGAs

    in PhD Forum, International Conference on Field-programmable Logic and Applications (FPL), 2015
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    PhD Forum, International Conference on Field-programmable Logic and Applications (FPL), 2015
  • Effective Learning and Filtering of Faulty Heart-Beats for Advanced ECG Arrhythmia Detection using MIT-BIH Database

    in Procedings of 5th International Conference on Wireless Mobile Communication and Healthcare (MOBIHEALTH), 2015
  • Job-Arrival Aware Distributed Run-Time Resource Management on Intel SCC Manycore Platform

    in Proceedings of 13th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC), 2015
    • Dimitris Rodopoulos ,
    • Simone Corbetta ,
    • Giuseppe Massari ,
    • Simone Libutti ,
    • Francky Catthoor ,
    • Yiannakis Sazeides ,
    • Chrysostomos Nicopoulos ,
    • Antoni Portero ,
    • Etienne Cappe ,
    • Radim Vavrik ,
    • Vit Vondrak ,
    • Dimitrios Soudris ,
    • Federico Sassi ,
    • Agnes Fritsch and
    • William Fornaciari

    HARPA: Solutions for Dependable Performance under Physically Induced Performance Variability

    in Proceedings of International Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), 2015
    • Dimitrios Soudris ,
    • Sotirios Xydis ,
    • Christos Baloukas ,
    • Anastasia Hadzidimitriou ,
    • Ioanna Chouvarda ,
    • Kostas Stamatopoulos ,
    • Nicos Maglaveras ,
    • John Chang ,
    • Andreas Raptopoulos ,
    • David Manset ,
    • Barbara Pierscionek ,
    • Reem Kayyali ,
    • Nada Phillip ,
    • Tobias Becker ,
    • Katerina Vaporidi ,
    • Eumorphia Kondili ,
    • Dimitrios Georgopoulos ,
    • Lesley-Ann Sutton ,
    • Richard Rosenquist ,
    • Lydia Scarfo and
    • Paolo Ghia

    AEGLE: A Big Bio-Data Analytics Framework for Integrated Health-Care Services

    in Proceedings of International Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), 2015
  • Platform-aware Dynamic Data Type Refinement Methodology for Radix Tree Data Structures

    in Proceedings of International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS), 2015
  • An Energy Efficient Message Passing Synchronization Algorithm for Concurrent Data Structures in Embedded Systems

    in Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems (SCOPES), 2015
  • Smart PV Module Topology with a Snake-Like Configuration

    in PVSEC 2015, 30th European Photovoltaic Solar Energy Conference and Exhibition (EU PVSEC), 2015
  • PV Energy Yield Nowcasting Combining Sky Imaging with Simulation Models

    in PVSEC 2015, 30th European Photovoltaic Solar Energy Conference and Exhibition (EU PVSEC), 2015
  • Scenario Modeling of Containership Liner-Shipping Operation Scheduling

    in European Conference on Shipping, Intermodalism & Ports (ECONSHIP), 2015
    • Dimitrios Stamoulis ,
    • Dimitris Rodopoulos ,
    • Brett H. Meyer ,
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    • Francky Catthoor and
    • Zeljko Zilic

    Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models

    in Proc. of of the 25th edition on Great Lakes Symposium on VLSI (GLSVLSI), 2015
  • Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach

    in Proceedings of the 11th International Symposium on Applied Reconfigurable Computing (ARC), 2015
  • SWAN-iCARE project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring

    in Proceedings of the 11th International Symposium on Applied Reconfigurable Computing (ARC), 2015
  • SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms

    in Proceedings of the 11th International Symposium on Applied Reconfigurable Computing (ARC), 2015
  • A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware

    in Proceedings of the 11th International Symposium on Applied Reconfigurable Computing (ARC), 2015
  • Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures

    in Proceedings of the 11th International Symposium on Applied Reconfigurable Computing (ARC), 2015
  • TEAChER: TEach AdvanCEd Recongurable architectures and tools

    in Proceedings of the 11th International Symposium on Applied Reconfigurable Computing (ARC), 2015
  • A Reconfigurable MapReduce Accelerator for multi-core all-programmable SoCs

    in Proceedings of International Symposium on Systemon-Chip (SOC), 2014
  • A HW/SW Framework Emulating Wearable Devices For Remote Wound Monitoring and Management

    in Proceedings of 4th International Conference on Wireless Mobile Communication and Healthcare (MOBIHEALTH), 2014
  • Hardware Accelerated Rician Denoise Algorithm for High Performance Magnetic Resonance Imaging

    in 4th International Conference on Wireless Mobile Communication and Healthcare (MOBIHEALTH), 2014
  • A MapReduce framework implementation for Network-on-Chip platforms

    in 21st IEEE International Conference on Electronics Circuits and Systems (ICECS), 2014
    • Dimitrios Stamoulis ,
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    Linear Regression Techniques for Efficient Analysis of Transistor Variability

    in Proceedings of 21st IEEE International Conference on Electronics Circuits and Systems (ICECS), 2014
  • Reconfigurable FEC Codes for Software-defined Optical Transceivers

    in Proceedings of 13th International Conference on Optical Communications and Networks (ICOCN), 2014
  • Evaluation of Message Passing Synchronization Algorithms in Embedded Systems

    accepted for presentation in International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS), 2014
  • Demonstration and validation of an energy yield prediction model suitable for non-steady state non-uniform conditions

    in 6th World Conference on Photovoltaic Energy Conversion (WCPEC), 2014
  • Presentation of a Verilog-AMS Model for Detailed Transient Electro-Thermal Simulations of PV Modules and Systems

    in Proceedings of 29th European Photovoltaic Solar Energy Conference and Exhibition (EU PVSEC), 2014
  • Configurable Module Topology to Recover Power Lost due to Current Mismatch

    in Proceedings of 29th European Photovoltaic Solar Energy Conference and Exhibition (EU PVSEC), 2014
  • Optimal Mapping of Inferior Olive Neuron Simulations on the Single-Chip Cloud Computer

    in Proceedings of International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS), 2014
    • Dimitris Rodopoulos ,
    • George Stamoulis ,
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    • Grigorios Lyras

    Understanding Timing Impact of BTI/RTN with Massively Threaded Atomistic Transient Simulations

    in Proceedings of International Conference on IC Design and Technology (ICICDT), 2014
  • A Framework for Customizing Virtual 3-D Reconfigurable Platforms at Run-Time

    in Proceedings of 21st Reconfigurable Architectures Workshop (RAW), 2014
  • Framework for Mapping Dynamic Virtual Kernels onto Heterogeneous Reconfigurable Platforms

    in Proceedings of 21st Reconfigurable Architectures Workshop (RAW), 2014
  • A Low-Latency Algorithm and FPGA Design for the Min-Search of LDPC Decoders

    in Proceedings of 21st Reconfigurable Architectures Workshop (RAW), 2014
  • Effective Platform-Level Exploration for Heterogeneous Multicores Exploiting SimulationInduced Slacks

    in PARMA-DITAM 2014 Workshop, 5th Workshop on Parallel Programming and RunTime Management Techniques for Many-core Architectures - 3rd Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2014
  • A Configurable MapReduce Accelerator for Multi-core FPGAs

    in Proceedings of 22nd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2014
  • A New Design Paradigm for Floating-Point DSP Applications Based on ESL/HLS and FPGAs

    in IEEE International Symposium on Signal Processing and Information Technology (ISSPIT), 2013
  • Automatic Implementation of Low-Complexity QC-LDPC Encoders

    in Proceedings of 23th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2013
  • A Platform-Independent Runtime Methodology For Mapping Multiple Applications Onto Fpgas Through Resource Virtualization

    in 23rd International Conference on Field Programmable Logic and Applications (FPL), 2013
  • A Low-Complexity Implementation of QC-LDPC Encoder In Reconfigurable Logic

    in 23rd International Conference on Field Programmable Logic and Applications (FPL), 2013
    • Isabelle Texier ,
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    • Marie Muller ,
    • Pierre-Yves Benhamou ,
    • Marc Correvon ,
    • Gabriela Dudnik ,
    • Guy Voirin ,
    • Natascha Bue ,
    • Jan Cristensen ,
    • Massimo Laurenza ,
    • Giuseppe Gazzara ,
    • Andreas Raptopoulos ,
    • Alexandros Bartzas ,
    • Dimitrios Soudris ,
    • Carl Saxby ,
    • Thierry Navarro ,
    • Fabio di Francesco ,
    • Pietro Salvo ,
    • Marco Romanelli ,
    • Battistino Paggi and
    • Leonidas Lymperopoulos

    SWAN-iCare: A smart wearable and autonomous negative pressure device for wound monitoring and therapy

    in Proceedings of 13th International Conference on Embedded Computer ystems: Architectures, Modeling, and Simulation (SAMOS), 2013
  • A Process-Based Reconfigurable SystemC Module for Simulation Speedup

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  • On Supporting Adaptive Fault Tolerant at Run-Time with Virtual FPGAs

    in Proceedings of the Workshop on Virtual Prototyping of Parallel and Embedded Systems (ViPES), 2013
  • HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips

    in Proceedings of the Workshop on Virtual Prototyping of Parallel and Embedded Systems (ViPES),2013
  • Distributed run-time resource management for malleable applications on many-core platforms

    in Proceedings of Design Automation Conference (DAC), 2013
  • Adaptive memory management for applications of highly-varying runtime requirements

    in Proceedings of PARMA Workshop, 2013
  • A Framework for Supporting Parallel Application Placement onto Reconfigurable Platforms

    in Proceedings of PARMA Workshop, 2013
  • Hypervised transient SPICE simulations of large netlists & workloads on multi-processor systems

    in Design, Automation & Test in Europe (DATE), 2013
  • FPGA-based Path-planning of High Mobility Rover for Future Planetary Missions

    in Proc. 19th IEEE International Conference on Electronics, Circuits, and Systems, 2012
  • Performance Evaluation of Embedded Processor in MapReduce Cloud Computing Applications

    in Proccedings of 3rd International Conference on Cloud Computing (CLOUDCOMP), 2012
    • Dimitris Bekiaris ,
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    Run-Time Measurement of Harvested Energy for Autarkic Sensor Operation

    in Proccedings of 22th Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2012
    • Dimitris Bekiaris ,
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    Systematic design and evaluation of a scalable reconfigurable multiplier scheme for HLS environments

    in Proceedings of Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2012
    • Anastasia Garbi ,
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    NEPHRON+: ICT-enabled wearable artificial kidney and personal renal care system

    in Proceedings of 7th International Conference on "Communications, Electromagnetics and Medical Applications (CEMA), 2012
  • On Designing Self-Aware Reconfigurable Platforms

    in Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012
  • Hardware Implementation of Stereo Correspondence Algorithm for the Exomars Mission

    in Proccedings of Field Programmable Logic (FPL), 2012
  • Adaptive dynamic memory allocators by estimating application workloads

    in Proceedings of Special Session on Programming Paradigms for Reconfigurable Multi-Core Embedded Systems (SAMOS), 2012
  • SPARTAN Project: On Profiling Computer Vision Algorithms for Rover Navigation

    in Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2012
  • A low-cost fault tolerant solution targeting to commercial FPGA devices

    in Special Session “Dependability by reconfigurable hardware” in Proc. of NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2012
  • On Supporting Efficient Partial Reconfiguration with Just-In-Time Compilation

    in Proceedings of RAW 9th Reconfigurable Architectures Workshop, 2012
  • “Software Mitigation of Transient Errors on the Single-Chip Cloud Computer

    in SELSE 2012, Silicon Errors in Logic - System Effects, 2012
  • Run-Time Dynamic Data Type Transformations

    in PARMA Workshop, 2012
  • Efficient Memory Allocations on a ManyCore Accelerator

    in PARMA Workshop, 2012
  • A Divide and Conquer based Distributed Run-time Mapping Methodology for Many-Core platforms

    in Proceedings of Design Automation and Test in Europe (DATE), 2012
    • Cristina Silvano ,
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    • Diego Melpignano ,
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    • B. Stabernack ,
    • J. Brandenburg ,
    • M. Palkovic ,
    • Chantal Ykman-Couvreur ,
    • Alexandros Bartzas ,
    • Dimitrios Soudris ,
    • T. Kempf ,
    • G. Ascheid ,
    • H. Meyr ,
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    • P. Mahonen and
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    Parallel programming and Run-time Resource Management Framework for Many-core Platforms: The 2PARMA Approach

    in 6th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip (NA-OCMC), 2012
  • “The SPARTAN Project: FPGA-based Implementation of Computer Vision Algorithms Targeting to Space Applications”

    PAnhellenic Conference on Electronics and Telecommunications (PACET), 2011, Greece
  • Custom Memory Allocation on Platform 2012 – The 2PARMA Approach

    in P2012 developers' conference, 2011
    • Dimitris Bekiaris ,
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    • Efstathios Sotiriou-Xanthopoulos and
    • Dimitrios Soudris

    Low-Power Reconfigurable Component Utilization in a High-Level Synthesis Flow

    in Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2011
    • Efstathios Sotiriou-Xanthopoulos ,
    • Dionisis Diamantopoulos ,
    • George Economakos and
    • Dimitrios Soudris

    Design and Experimentation with Low-Power Morphable Multipliers

    in Proceedings of 18th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2011
  • Configurable Baseband Digital Transceiver for Gbps Wireless 60 GHz Communications

    in Proceedings of 18th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2011
    • Filippos Toufexis ,
    • Antonis Papanikolaou ,
    • Dimitrios Soudris ,
    • George Stamoulis and
    • Sotiris Bantas

    Power, Performance and Area Prediction of 3D ICs during Early Stage Design Exploration in 45nm

    in Proceedings of 18th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2011
  • A Framework for Architecture-Level Exploration of 3-D FPGA Platforms

    in Proc. of 21th International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS), 2011
  • Εnabling Efficient System Configurations For Dynamic Wireless Baseband Engines Using System Scenarios

    in Procedings of IEEE Workshop on Signal Processing Systems (SIPS), 2011
  • SPARTAN Project: Efficient Implementation of Computer Vision Algorithms onto Reconfigurable Platform Targeting to Space Applications

    in Proceedings of 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2011
    • Cristina Silvano ,
    • William Fornaciari ,
    • S. Crespi Reghizzi ,
    • G. Agosta ,
    • G. Palermo ,
    • V. Zaccaria ,
    • Patrick Bellasi ,
    • F. Castro ,
    • Simone Corbetta ,
    • E. Speziale ,
    • Diego Melpignano ,
    • J.M. Zins ,
    • H. Hubert ,
    • B. Stabernack ,
    • J. Brandenburg ,
    • M. Palkovic ,
    • P. Raghavan ,
    • Chantal Ykman-Couvreur ,
    • Iraklis Anagnostopoulos ,
    • Alexandros Bartzas ,
    • Dimitrios Soudris ,
    • T. Kempf ,
    • G. Ascheid ,
    • H. Meyr ,
    • J. Ansari ,
    • P. Mahonen and
    • B. Vanthournout

    Parallel programming and Run-time Resource Management Framework for Many-core Platforms: The 2PARMA Approach

    in Proceedings of 6th International Workshop on Reconfigurable Communication-centric Systems-onChip (ReCoSoC), 2011
    • Cristina Silvano ,
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    • G. Palermo ,
    • V. Zaccaria ,
    • Patrick Bellasi ,
    • F. Castro ,
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    • E. Speziale ,
    • Diego Melpignano ,
    • J.M. Zins ,
    • H. Hubert ,
    • B. Stabernack ,
    • J. Brandenburg ,
    • M. Palkovic ,
    • P. Raghavan ,
    • Chantal Ykman-Couvreur ,
    • Alexandros Bartzas ,
    • Dimitrios Soudris ,
    • T. Kempf ,
    • G. Ascheid ,
    • H. Meyr ,
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    • B. Vanthournout

    Parallel Paradigms and Run-time Management Techniques for Many-core Architectures: The 2PARMA Approach

    in Proceedings of IEEE 9th International Conference on Industrial Informatics (INDIN), 2011
  • A Methodology and Tool Framework For Supporting Rapid Exploration Of Memory Hierarchies In FPGAs

    in Proceedings of 21st International Conference on Field Programmable Logic and Applications (FPL), 2011
  • A Framework For Architecture-Level Exploration οf Communication Intensive Applications Onto 3-D FPGAs

    in Proceedings of 21st International Conference on Field Programmable Logic and Applications (FPL), 2011
  • Runtime Resource Management Techniques for Many-core Architectures: The 2PARMA Approach

    in Proceedings of the International Conference on ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS (ERSA), 2011
  • Thermal optimization for micro-architectures through selective block replication

    in Proceedings of Int. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), 2011
    • Dimitris Rodopoulos ,
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    Time and Workload Dependent Device Variability in Circuit Simulations

    in Proccedings of IEEE International Conference on IC Design and Technology, 2011
  • A heterogeneous Multicore System on Chip with run-time reconfigurable virtual FPGA Architecture

    in Proc. of 8th Reconfigurable Architectures Workshop (RAW), 2011
  • Quick_Hotspot: A Software Supported Methodology for Supporting Run-Time Thermal Analysis at MPSoC Designs

    in Proceedings of 2nd PARMA Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures, 2011
  • Runtime Tuning of Dynamic Memory Management For Mitigating Footprint-Fragmentation Variations

    in Proceedings of 2nd PARMA Workshop on Parallel Programming and Run-Time Management Techniques for Manycore Architectures, 2011
  • Trading Fault-Masking with Performance Overhead for FPGAs

    in Proceedings of 1st Workshop on Software-Controlled, Adaptive Fault-Tolerance in Microprocessors (SCAFT), 2011
  • A Novel Methodology for Architecture-Level Exploration of 3D SoCs

    in Proceedings of 6th International conference on Design & Technology of Integrated Systems in nanoscale era (DTIS), 2011
  • A Reconfigurable IP Characterization Technique Improving High-Level Synthesis Results

    in Proceedings of 6th International conference on Design & Technology of Integrated Systems in nanoscale era (DTIS), 2011
  • A standard cell library suite for deep-deep sub-micron CMOS technologies

    in Proceedings of 6th International conference on Design & Technology of Integrated Systems in nanoscale era (DTIS), 2011
  • CAD Tools for Designing 3D Integrated Systems

    in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), 2011
  • Bit-Width Exploration over 3D Architectures Using High-Level Synthesis

    in Proc. of 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2010
  • NAROUTO: An Open-Source Framework For Supporting Architecture-Level Exploration at Heterogeneous FPGAS

    in Proc. of 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2010
  • Multiple Vdd on 3D NoC Architectures

    in Proc. of 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2010
  • An Automatic Framework for Dynamic Data Structures Optimization in C

    in Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC), 2010
  • A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework

    in Proc. of PATMOS 2010, International Workshop on Power And Timing Modeling, Optimization and Simulation, 2010
  • Custom Multi-Threaded Dynamic Memory Management for Multiprocessor System-on-Chip Platforms

    in Proceedings - 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2010
  • High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures

    in Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2010
    • Christos Baloukas ,
    • Lazaros Papadopoulos ,
    • Dimitrios Soudris ,
    • S. Stuijk ,
    • O. Jovanovic ,
    • F. Schmoll ,
    • D. Cordes ,
    • R. Pyka ,
    • A. Mallik ,
    • Stylianos Mamagkakis ,
    • F. Capman ,
    • S. Collet ,
    • N. Mitas and
    • D. Kritharidis

    Mapping embedded applications on MPSoCs: the MNEMEE approach

    in Proceedings IEEE Symposium ISVLSI, 2010
    • Cristina Silvano ,
    • William Fornaciari ,
    • S. Crespi Reghizzi ,
    • G. Agosta ,
    • G. Palermo ,
    • V. Zaccaria ,
    • F. Castro ,
    • Simone Corbetta ,
    • A. Di Biagio ,
    • E. Speziale ,
    • M. Tartara ,
    • D. Siorpaes ,
    • H. Hubert ,
    • B. Stabernack ,
    • J. Brandenburg ,
    • M. Palkovic ,
    • P. Raghavan ,
    • Chantal Ykman-Couvreur ,
    • Alexandros Bartzas ,
    • Sotirios Xydis ,
    • Dimitrios Soudris ,
    • T. Kempf ,
    • G. Ascheid ,
    • R. Leupers ,
    • H. Meyr ,
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    A Framework For Automatic Parallelization, Static And Dynamic Memory Optimization in MPSOC Platforms

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  • Designing Efficient DSP Datapaths Through Compiler-in-the-Loop Exploration Methodology

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    in Proc. of 6th International Symposium on Applied Reconfigurable Computing (ARC), 2010
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    Dynamic Data Type Optimization and Memory Assignment Methodologies

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    Compilation Technique for Loop Overhead Minimization

    in Euromicro Conference on Digital System Design (DSD), 2009
  • DSP implementations on alternative NoC architectures

    in Proc. Of 16th International Conference on Digital Signal Processing (DSP), 2009
  • Three dimensional FPGA Architectures: A Shift Paradigm for Energy performance efficient DSP implemenentations

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  • An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs

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  • Mapping DSP Applications onto HighPerformance Architectural Templates with Inlined Flexibility

    in Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2008
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    Enabling RunTime Memory Data Transfer Optimizations at the System Level with Automated Extraction of Embedded Software Metadata Information

    in Proceedings of 13th Asia and South Pacific Design Automation Conference (ASP-DAC), 2008
  • MEANDER: A CAD Tool Framework for Designing 2D/3D FPGAs

    Third International Conference “Micro&Nano2007” on Micro-Nanoelectronics, Nanotechnology and MEMs, NCSR Demokritos, Athens, 18 – 21 November 2007
  • GNS: A Tool for the Analysisof Gene Regulatory Networks

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  • Application-domain-specific Reconfigurable FPGA Platform: An Integrated Hardware and Software Design Approach

    in Ph.D. Forum, Proc. of VLSI-SOC, IFIP Int. Conference on Very Large Scale Integration, 2007
  • Exploration of Alternative Topologies for Application Specific 3D Networks on Chip

    in Proceedings of Workshop on Application Specific Processors (WASP), 2007
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    in Proc. of 5th Workshop on Embedded Systems for Real-Time Multimedia (ESTIMEDIA), 2007
  • Dynamic Data Structure Exploration of Dynamic Applications

    in Proc. of PACT 2007, The Sixteenth International Conference on Parallel Architectures and Compilation Techniques (PACT), 2007
  • A Software-Supported Methodology for Desinging High-Performance 3D FPGA Architectures

    in Proc. of VLSI-SOC, IFIP Int. Conference on Very Large Scale Integration, 2007
  • Implementing Cellular Automata Modeled Applications into Network-on-Chip Platform

    in Proc. of VLSI-SOC, IFIP Int. Conference on Very Large Scale Integration, 2007
  • Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support

    in Proc. of FPL 2007, 17th Int. Conference on Field Programmable Logic and Applications, 2007
  • System-Level Application-specific NoC design for Network and Multimedia applications

    in Proceedings of 17th International Workshop, Power and Timing Modeling, Optimization and Simulation (PATMOS), 2007
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    • Dimitrios Soudris

    Direct memory access optimization in wireless terminals for reduced memory latency and energy consumption

    in Proceedings of 17th International Workshop, Power and Timing Modeling, Optimization and Simulation (PATMOS), 2007
  • Design Methodology and Software tool for Estimation of Multi-level Instruction Cache Memory Miss Rate

    in Proc. of 17th International Workshop, Power and Timing Modeling, Optimization and Simulation (PATMOS), 2007
  • Optimal Data Structure Exploration for Multimedia and Network Applications in Embedded Systems

    in IC-SAMOS - International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2007
  • A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs

    in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2007
  • Application – specific NoC platform design based on System Level Optimization

    in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2007
  • Optimization of Dynamic Data Structures in Multimedia Embedded Systems Using Evolutionary Computation

    in Proceedings of 10th International Workshop on Software and Compilers for Embedded Systems (SCOPES), 2007
  • Designing Heterogeneous FPGAs with Multiple SBs

    International Workshop on Applied Reconfigurable Computing (ARC), 2007
  • A Temperature-Aware Mapping Methodology for FPGAs

    in Proc. of Fifteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2007
  • Middleware Design Optimization of Wireless Protocols Based on the Exploitation of Dynamic Input Patterns

    in Proc. of Design Automation & Test in Europe (DATE), 2007
  • An Estimation Methodology for Designing Instruction Cache Memory of Embedded Systems

    in Proceedings of ESTIMedia, 2006
  • Research Network for System Level Design of Embedded Systems: Dynamic Memory Allocation Design Flow Case Study

    in Proceedings of ACM Workshop on Embedded Systems Education (WESE), 2006
  • Energy efficient dynamic memory allocators at the middleware level of embedded systems

    in Proceedings of 6th Annual ACM Conference on Embedded Software (EMSOFT), 2006
  • Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources

    in 16th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2006
  • Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique

    in Proc. Of IFIP International Conference on VLSI –VLSISOC, 2006
  • Wire segment length and switch box co-optimization for FPGA architectures

    in Proc. of 15th Int. Conference on Field Programmable Logic and Applications (FPL), 2006
  • Modelling Gene Regulatory Networks using Cellular Automata

    in Proc. of 5 th European Symposium on BioMedical Engineering (ESBME), 2006
    • Alexandros Bartzas ,
    • Miguel Peon ,
    • Stylianos Mamagkakis ,
    • D. Atienza ,
    • Francky Catthoor ,
    • Dimitrios Soudris and
    • J. Mendias

    Systematic Design Flow for Dynamic Data Management in Visual Texture Decoder of MPEG-4

    in Proc. of 2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006
  • A Novel Methodology for Designing High-Performance and Low-Power FPGA Interconnection Targeting DSP Applications

    in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), 2006
  • Platform-based FPGA Architecture: Designing High-Performance and Low-Power Routing Structure for Realizing DSP Applications

    in Proc. of RAW 2006, 13th Reconfigurable Architectures Workshop, 2006
  • A Novel Methodology for Designing HighPerformance and Low-Energy FPGA Routing Architecture

    in Proc. of Fourteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2006
  • Automated Exploration of Pareto optimal Configurations in Parameterized Dynamic Memory Allocation for Embedded Systems

    in Proc. of Design Automation & Test in Europe (DATE), 2006
    • Alexandros Bartzas ,
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    • Stylianos Mamagkakis ,
    • D. Atienza ,
    • Francky Catthoor ,
    • Dimitrios Soudris and
    • Adonios Thanailakis

    Dynamic Data Type Refinement Methodology for Systematic Performance–Energy Design Exploration of Network Applications

    in Proc. of Designe Automation and Test in Europe (DATE), 2006
    • Nikolaos Kroupis ,
    • Nikos Zervas ,
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    • Adonios Thanailakis

    High-Level Performance and Power Exploration of DSP Applications Realized on Programmable Processors

    in Proc. of IEEE International Symposium on Signal Processing and Information Technology (ISSPIT), 2005
    • Alexandros Bartzas ,
    • G. Pouiklis ,
    • Stylianos Mamagkakis ,
    • Francky Catthoor ,
    • Dimitrios Soudris and
    • Adonios Thanailakis

    Performance Energy Trade-off Exploration in Dynamic Data Types for Network Applications

    in Proc. of IEEE International Symposium on Signal Processing and Information Technology (ISSPIT), 2005
    • Kostas Siozios ,
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    • I. Pappas ,
    • Dimitrios Soudris ,
    • Spyridon Nikolaidis ,
    • Stylianos Siskos and
    • Adonios Thanailakis

    The AMDREL Project in Retrospective

    in Proc. IFIP Inter. Conference in Very Large Scale Integration VLSI-SOC, 2005
    • Minas Dasigenis ,
    • Erik Brockmeyer ,
    • Francky Catthoor ,
    • Dimitrios Soudris and
    • Adonios Thanailakis

    Improving the Memory Bandwidth Utilization in Embedded Systems Using Loop Transformations

    in Proceedings of 15th International Workshop, Power and Timing Modeling, Optimization and Simulation (PATMOS), 2005
  • A Data and Instruction Memory Performance and Energy Optimization Technique

    in Proceedings of PRIME 2005, Ph.D. Research in Micro-Electronics & Electronics, 2005
  • A Low-Energy FPGA: Architecture Design and SoftwareSupported Design Flow

    in Proceedings of 14th Inter. Conference on Field Programmable Logic and Applications (FPL), 2005
  • An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform

    in Proceedings of 14th Inter. Conference on Field Programmable Logic and Applications (FPL), 2005
  • A Methodology for Partitioning DSP Applications in Hybrid Reconfigurable Systems

    in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), 2005
    • Stylianos Mamagkakis ,
    • Christos Mpaloukas ,
    • D. Atienza ,
    • Francky Catthoor ,
    • Dimitrios Soudris and
    • J. Mendias

    Reducing Memory Fragmentation with Performance-optimized Dynamic Memory Allocators in Network Applications

    in Proc. of 3 nd International Conf. on Wired/Wireless Internet Communications (WWIC), 2005
  • A Modified Spiral Search Motion Estimation Algorithm and its Embedded System Implementation

    in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), 2005
  • A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable Platforms

    in Proceedings of RAW 2005, 12th Reconfigurable Architectures Workshop, 2005
  • DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and its Software Tool Implementation

    in Proceedings of RAW 2005, 12th Reconfigurable Architectures Workshop, 2005
    • Dimitrios Soudris ,
    • Spyridon Nikolaidis ,
    • Stylianos Siskos ,
    • Konstantinos Tatas ,
    • Kostas Siozios ,
    • G. Koutroumpezis ,
    • N. Vasiliadis ,
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    • I. Pappas and
    • Adonios Thanailakis

    AMDREL: A Novel Low-Energy FPGA Architecture and Supporting CAD Tool Design Flow

    in Proc. of ASP-DAC 2005, Asia South Pacific – Design Automation Conference (Design Contest), 2005
    • Minas Dasigenis ,
    • Erik Brockmeyer ,
    • Bart Durinck ,
    • Francky Catthoor ,
    • Dimitrios Soudris and
    • Adonios Thanailakis

    A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck

    in Proceedings of Design Automation & Test in Europe (DATE), 2005
  • A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms

    in Proceedings of Design Automation & Test in Europe (DATE), 2005
    • I. Pappas ,
    • N. Vassiliadis ,
    • V. Kalenteridis ,
    • H. Pournara ,
    • Spyridon Nikolaidis ,
    • Stylianos Siskos ,
    • Kostas Siozios ,
    • G. Koutroumpezis ,
    • Konstantinos Tatas ,
    • Dimitrios Soudris and
    • Adonios Thanailakis

    Fine-Grain Reconfigurable Platform: FPGA Hardware Design and Software Toolset Development

    Proceedings of Microelectronics Microsystems and Nanotechnology, 14-17 November 2004, Greece
  • A High Performance DataPath to Accelerate DSP Kernels

    in Proceedings of 11th Int. Conf. on Electronics, Circuits and Systems (ICECS), 2004
  • Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path

    in Proc. of 14th International Workshop, Power and Timing Modeling, Optimization and Simulation (PATMOS), 2004
  • Reducing Memory Accesses with a System-Level Design Methodology in Customized Dynamic Memory Management

    in Proc. of ESTIMedia 2004, 2nd Workshop on Embedded Systems for Real-Time Multimedia, 2004
    • Stylianos Mamagkakis ,
    • D. Atienza ,
    • C. Poucet ,
    • Francky Catthoor ,
    • Dimitrios Soudris and
    • J. Mendias

    Custom Design of Multi-Level Dynamic Memory Management Subsystem for Embedded Systems

    in Proc. of IEEE Workshop on Signal Processing Systems (SIPS), 2004
    • D. Atienza ,
    • Stylianos Mamagkakis ,
    • M. Leeman ,
    • Francky Catthoor ,
    • J. Mendias and
    • Dimitrios Soudris

    Power-Aware Tuning of Dynamic Memory Management for Embedded Real-Time Multimedia Applications

    in Proceedings of 19th Conference on Design of Circuits and Integrated Systems, (DCIS), 2004
    • K. Masselos ,
    • S. Blionas ,
    • Jean-Yves Mignolet ,
    • A. Foster ,
    • Dimitrios Soudris and
    • Spyridon Nikolaidis

    Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform

    in Proc. of 14th International Workshop, Power and Timing Modeling, Optimization and Simulation (PATMOS), 2004
  • A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development

    in Proceedings of 13th International Conference on Field Programmable Logic and Applications (FPL), 2004
  • Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path

    in Proceedings of 13th International Conference on Field Programmable Logic and Applications (FPL), 2004
    • D. Atienza ,
    • Stylianos Mamagkakis ,
    • M. Leeman ,
    • Francky Catthoor ,
    • J. Mendias and
    • Dimitrios Soudris

    Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems

    in Proc. of 14th International Workshop, Power and Timing Modeling, Optimization and Simulation (PATMOS), 2004
    • Minas Dasigenis ,
    • Erik Brockmeyer ,
    • Bart Durinck ,
    • Francky Catthoor ,
    • Dimitrios Soudris and
    • Adonios Thanailakis

    Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications

    in Proc. of Workshop SAMOS IV: Systems, Architectures, MOdeling, and Simulation (SAMOS), 2004
  • A Novel Data-Path for Accelerating DSP Kernels

    in Proc. of Workshop SAMOS IV: Systems, Architectures, MOdeling, and Simulation (SAMOS), 2004
  • A Reconfigurable System-on-Chip Platform for Wireless Communications

    in Proc. of Workshop on Wireless Circuits and Systems (WoWCAS), 2004
  • Accelerating DSP Applications on a Mixed Granularity Platform with a new Reconfigurable Coarse-Grain Data-Path

    in Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2004
    • H. Pournara ,
    • V. Kalenteridis ,
    • I. Pappas ,
    • N. Vassiliadis ,
    • Spyridon Nikolaidis and
    • Dimitrios Soudris

    Energy Efficient Fine-Grain Reconfigurable Hardware

    in Proc. of 12th IEEE Mediterranean Electrotechnical Conference (MELECON), 2004
  • The Effect of the Interconnection Architecture on the FPGA Performance and Energy Consumption

    in Proceedings of 12th IEEE Mediterranean Electrotechnical Conference (MELECON), 2004
    • E. Theochari ,
    • Konstantinos Tatas ,
    • Dimitrios Soudris ,
    • K. Masselos ,
    • Konstantinos Potamianos ,
    • S. Blionas and
    • Adonios Thanailakis

    A Reusable IP FFT Core For DSP Applications

    in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), 2004
    • V. Kalenteridis ,
    • H. Pournara ,
    • Kostas Siozios ,
    • Konstantinos Tatas ,
    • I. Pappas ,
    • N. Vassiliadis ,
    • G. Koutroumpezis ,
    • Spyridon Nikolaidis ,
    • Stylianos Siskos ,
    • Dimitrios Soudris and
    • Adonios Thanailakis

    An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development

    in Proceedings of 11th Reconfigurable Architectures Workshop (RAW) , 2004
    • Stylianos Mamagkakis ,
    • A. Mpartzas ,
    • G. Pouiklis ,
    • D. Atienza ,
    • Francky Catthoor ,
    • Dimitrios Soudris and
    • J. Mendias

    Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology

    in Proc. 2nd International Conf. on Wired/Wireless Internet Communications (WWIC), 2004
  • A Novel Coarse-Grain Reconfigurable Data-Path for Accelerating DSP Kernels

    in 12th ACM International Symposium on Field-Programmable Gate Arrays (FPGA), 2004
  • Dynamic Memory Management Design Methodology for Reduced Memory Footprint in Multimedia and Wireless Network Applications

    in Proc. of Design Automation & Test in Europe (DATE), 2004
  • Designing Low Power Direct Digital Frequency Synthesizers

    in Proc. of IFIP Inter. Conference in Very Large Scale Integration VLSI-SOC, 2003
    • D. Atienza ,
    • Stylianos Mamagkakis ,
    • M. Leeman ,
    • Francky Catthoor ,
    • J. Mendias ,
    • Dimitrios Soudris and
    • G. Deconinck

    Fast System-Level Prototyping of Power-Aware Dynamic Memory Managers for Embedded Systems

    in proc. of Workshop on Compilers and Operating Systems for Low Power (COLP), 2003
    • Minas Dasigenis ,
    • Erik Brockmeyer ,
    • Dimitrios Soudris ,
    • Francky Catthoor ,
    • Adonios Thanailakis and
    • G. Papakostas

    Performance and Energy Optimization of Multimedia Applications using DMA Combined with Prefetch

    in proc. of Workshop on Compilers and Operating Systems for Low Power (COLP), 2003
  • FPGA Architecture Design and Toolset for Logic Implementation

    in 13th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2003
  • Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms

    in 13th International Conference on Field Programmable Logic and Applications, 2003
  • Power Optimization Methodology for Multimedia Applications Implementation on Reconfigurable Platforms

    in 13th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2003
  • Alternative Direct Digital Frequency Synthesizer Architectures with Reduced Memory Size

    in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), 2003
    • Dimitrios Soudris ,
    • K. Sgouropoulos ,
    • Konstantinos Tatas ,
    • Vasilis Pavlidis and
    • Adonios Thanailakis

    A Methodology for Implementing FIR Filters and CAD Tool Development for Designing RNS-Based Systems

    in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), 2003
  • Performance and Power Comparative Study of Discrete Wavelet Transform on Programmable Processors

    in 12th Inter. Workshop Power and Timing Modeling, Optimization and Simulation (PATMOS), 2002
    • G. Koutroumpezis ,
    • Konstantinos Tatas ,
    • Dimitrios Soudris ,
    • S. Blionas ,
    • K. Masselos and
    • Adonios Thanailakis

    Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-grain Applications

    in 12th International Conference on Field Programmable Logic and Applications (FPL), 2002
  • A Window-Based Color Quantization Technique and Its Embedded Implementation

    in Proc. of IEEE Int. Conference on Image processing (ICIP), 2002
  • A Color Quantization Technique Based on Image Decomposition and its Hardware Implementation

    in Proceedings of IASTED International Conference, Signal Processing, Pattern, Recognition, and Applications, (SPPRA), 2002
  • A Novel Division Algorithm for Parallel and Sequential Processing

    in Proc. of IEEE 9th Int. Conf. on Electronics, Circuits and Systems (ICECS), 2002
    • Dimitrios Soudris ,
    • Minas Dasigenis ,
    • K. Mitroglou ,
    • Konstantinos Tatas and
    • Adonios Thanailakis

    A Full Adder Based Methodology for Scaling Operation in Residue Number System

    in Proc. of 9th Int. Conf. on Electronics, Circuits and Systems (ICECS), 2002
    • Dimitrios Soudris ,
    • K. Masselos ,
    • S. Blionas ,
    • Stylianos Siskos ,
    • Spyridon Nikolaidis ,
    • Konstantinos Tatas and
    • Jean-Yves Mignolet

    AMDREL: Designing Embedded Reconfigurable Hardware Structures for Future Reconfigurable Systems-on-Chip for Wireless Communication Applications

    in Proceedings of IEEE Workshop on Heterogeneous Reconfigurable Systems on Chip (SOC), 2002
  • A Window-Based Color Quantization Technique and its Architecture Implementation

    in Proc. of 14th International Conference on Digital Signal Processing (DSP), 2002
    • A. Kakarountas ,
    • K. Papadomanolakis ,
    • Spyridon Nikolaidis ,
    • Dimitrios Soudris and
    • Costas Goutis

    Confronting Violations Of The TSCG(T) In Low-Power Design

    in Proc. Int. Symp. Circuits and Systems (ISCAS), 2002
  • A Code Transformation-Based Methodology for Improving I-Cache Performance of Multimedia Applications

    In Proceedings of Design Automation & Test in Europe (DATE), 2002
  • The Low Power Baseband Processing Parts of a Novel Dual Mode DECT/GSM Terminal

    In Proc. of 8th Int. Conf. on Electronics, Circuits and Systems (ICECS), 2001
  • Designing Low-Power Energy Recovery Adders Based On Pass Transistor Logic

    In Proc. of 8th Int. Conf. on Electronics, Circuits and Systems (ICECS), 2001
    • Nikolaos Kroupis ,
    • Minas Dasigenis ,
    • A. Argyriou ,
    • Konstantinos Tatas ,
    • Dimitrios Soudris ,
    • Adonios Thanailakis and
    • Costas Goutis

    Power, Performance and Area Exploration of Block Matching Algorithms Mapped on Programmable Processors

    In IEEE Int. Conference on Image processing (ICIP), 2001
    • Minas Dasigenis ,
    • Nikolaos Kroupis ,
    • A. Argyriou ,
    • Konstantinos Tatas ,
    • Dimitrios Soudris and
    • Nikos Zervas

    Data And Instruction Memory Exploration Of Embedded Systems For Multimedia Application

    In Proc. of IEEE International Conference on Acoustics, Speech, and Signal Processing ( ICASSP), 2001
    • Minas Dasigenis ,
    • Nikolaos Kroupis ,
    • A. Argyriou ,
    • Konstantinos Tatas ,
    • Dimitrios Soudris ,
    • Nikos Zervas and
    • Adonios Thanailakis

    A Memory Management Approach For Efficient Implementation Of Multimedia Kernels On Programmable Architectures

    In Proc. of IEEE Computer Society Annual Workshop on VLSI (WVLSI), 2001
  • On the Implementation o f A Baseband Processor For A Portable Dual Mode DECT/GSM Terminal

    In Proc. of Int. Symp. Circuits and Systems, 2001
  • A CAD tool for architecture level exploration and automatic generation of RNS converters

    In Proc. of Int. Symp. On Circuits and Systems (ISCAS). 2001
  • The Circuit Design of Multiple-Valued Logic Voltage-Mode Adders

    In Proc. of Int. Symp. On Circuits and Systems (ISCAS). 2001
  • Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores

    In Proc. of IEEE International Symposium on Quality Electronic Design, 2001
  • “On the Design of a Low Power Modulator/Demodulator for DECT/GSM”

    Proc. of 1 st Conf. Microelectronics, Microsystems, & Nanotechnology, November 20-22, 2000, Athens
  • “The Design Of A Ripple Carry Adiabatic Adder”

    Proc. of 1 st Conf. Microelectronics, Microsystems, & Nanotechnology, November 20-22, 2000, Athens
  • “A CAD Tool For Automatic Generation of RNS & QRNS Converters”

    Proc. of 1 st Conf. Microelectronics, Microsystems, & Nanotechnology, November 20-22, 2000, Athens
  • Data-reuse exploration of multimedia applications on programmable processor cores

    In Proc. in XVth Conference on Design of Circuits and Integrated Systems (DCIS), 2000
  • A novel algorithm for division

    In Proc. in XVth Conference on Design of Circuits and Integrated Systems (DCIS), 2000
    • Nikos Zervas ,
    • S. Theoharis ,
    • A. Kakarudas ,
    • Sergios Theodoridis ,
    • Dimitrios Soudris and
    • Costas Goutis

    Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers

    In Proc. of 10th Int. Workshop Power And Timing Modeling, Optimization And Simulation (PATMOS). 2000
    • Dimitrios Soudris ,
    • Nikos Zervas ,
    • A. Argyriou ,
    • Minas Dasigenis ,
    • Konstantinos Tatas ,
    • Costas Goutis and
    • Adonios Thanailakis

    Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Application

    In Proc. of 10th Int. Workshop Power And Timing Modeling, Optimization And Simulation (PATMOS), 2000
  • A Methodology for the Behavioral – Level Event – Driven Power Management of Digital Receivers

    In Proc. of Int. Symp. on Circuits and Systems (ISCAS). 2000
    • Dimitrios Soudris ,
    • Minas Perakis ,
    • X. Mizas ,
    • Vassilios Mardiris ,
    • C. Katis ,
    • C. Dre ,
    • Apostolos Tzimas ,
    • Emmanuel Metaxakis ,
    • Grigorios Kalivas ,
    • Nikos Zervas ,
    • S. Theoharis ,
    • George Theodoridis ,
    • Adonios Thanailakis and
    • Costas Goutis

    Low-Power Design of A Multi-Mode Transceiver

    In Proc. of Int. Symp. on Circuits and Systems (ISCAS), 2000
  • Designing RNS and QRNS Full A dder Based Converters

    In Proc. of Int. Symp. on Circuits and Systems (ISCAS), 2000
    • Nikos Zervas ,
    • Minas Perakis ,
    • Dimitrios Soudris ,
    • C. Dre ,
    • Costas Goutis and
    • Adonios Thanailakis

    A Low Power GMSK/GFSK MoDem

    In Proc. of ESDLPD'00, Third International Workshop of the European Low Power Initiative for Electronic System Design, 2000
    • Dimitrios Soudris ,
    • Nikos Zervas ,
    • Minas Perakis ,
    • S. Theoharis ,
    • George Theodoridis ,
    • Grigorios Kalivas ,
    • C. Dre ,
    • Costas Goutis and
    • Adonios Thanailakis

    On the Low Power Design of Digital Receivers for Wireless Applications

    In Proc. of DATE 2000 User Forum, 2000
  • A Modified Energy Recovery Technique For Implementing DSP Algorithm

    In Proc. of 9th Int. W orkshop Power And Timing Modeling, Optimization And Simulation (Patmos), 1999
  • A New Adiabatic Technique for Designing Low Power Array Architectures

    In Proc. of Int. Conf. on Electronics, Circuits and Systems (ICECS), 1999
  • The design of low power multiple-valued logic encoder and decoder circuits

    In Proc. of Int. Conf. on Electronics, Circuits and Systems (ICECS), 1999
  • Estimation of Power Dissipation in Glitching Using Complex-Time Cellular Automata

    In Proc. of Int. Conf. on Electronics, Circuits and Systems (ICECS), 1999
  • An Efficient Probabilistic Method for Logic Circuits Using Real Delay Gate Model

    In Int. Symp. on Circuits and Systems (ISCAS), 1999
    • Minas Perakis ,
    • Apostolos Tzimas ,
    • Emmanuel Metaxakis ,
    • Dimitrios Soudris ,
    • Grigorios Kalivas ,
    • C. Katis ,
    • C. Dre ,
    • Costas Goutis and
    • Adonios Thanailakis

    The VLSI Implementation of a Baseband Receiver For DECT-Based Portable Applications

    In Int. Symp. on Circuits and Systems (ISCAS), 1999
    • Georgios Sirakoulis ,
    • Ioannis Karafyllidis ,
    • Dimitrios Soudris ,
    • Nikolaos Georgoulas and
    • Adonios Thanailakis

    An Oxidation Process simulator for TCAD

    In Proc. of 20th Inter. Spring Seminar on Semiconductor and Hybrid Technologies, 1998
  • Accurate Data Path Models For RT-Level Power Estimation

    In Proc. of 8th Int. Workshop Power and Timing Modeling, Optimization and Simulation, 1998
    • I. Thoidis ,
    • Dimitrios Soudris ,
    • Ioannis Karafyllidis ,
    • Adonios Thanailakis and
    • Thanos Stouraitis

    Methodology for Designing Multiple-Valued Logic Voltage-Mode Circuit

    In Proceedings of IEEE Int. Symp. on Circuits and Systems (ISCAS), 1998
    • I. Thoidis ,
    • Dimitrios Soudris ,
    • Ioannis Karafyllidis ,
    • Adonios Thanailakis and
    • Thanos Stouraitis

    Multiple-Valued Logic Voltage-Mode Storage Circuits Based on True-Single-Phase Clocked Logic

    In Proc. of 8th IEEE Great Lakes Symposium on VLSI, 1998
  • A New Method for Switching Activity Estimation of Logic Level Networks

    In Proc. of 7th Int. W orkshop Power and Timing Modeling, Optimization and Simulation (PATMOS), 1997
    • George Theodoridis ,
    • S. Theoharis ,
    • Dimitrios Soudris ,
    • Odysseas Koufopavlou and
    • Costas Goutis

    A Novel Approach for Reducing the Switching Activity in Two-level Logic Circuits

    In Proc. of 3rd IEEE Int . Conf. on Electronics, Circuits, and Systems (ICECS), 1996
  • Low – Power Design of Array Architectures

    In Proc. of 3rd IEEE Int. Conf. on Electronics, Cir cuits, and Systems (ICECS), 1996
  • Systematic Design of Novel Architectures of Radon Transform

    In Proc. of 38th IEEE Midwest Symposium of Circuits and Systems, 1995
  • Designing Efficient Redundant Arithmetic Processors for DSP applications

    In Proc. of 38th IEEE Midwest Symposium of Circuits and Systems, 1995
  • A Petri Net approach to the Design of Processor Array Architecture

    In Proc. of 38th IEEE Midwest Symposium of Circuits and Systems, 1995
  • A Systematic Methodology for Designing Multilevel Systolic Architecture

    In Proc. of IEEE Inter. Conf. On Circuits and Systems (ISCAS), 1993
  • Methodology for the Design of Signed – Digit DSP Processors

    In Proc. of Inter. Conf. On Circuits and Systems (ISCAS), 1993
    • Dimitrios Soudris ,
    • Vassilis Paliouras ,
    • Thanos Stouraitis ,
    • Alexander Skavantzos and
    • Costas Goutis

    Systematic Design of Full Adder – Based Architectures for Convolution

    In Proc. of IEEE Inter. Conf. on Acoustics, Speech, and Signal Processing (ICASSP), 1993
  • Systematic Development of Architectures for Multidimensional DSP Using the Residue Number System

    In Proc. of IEEE Inter. Conf. on Acoustics, Speech, and Signal Processing (ICASSP), 1992
  • Systematic Derivation of the processing Element of a Systolic Array based on Residue Number System

    In Proc. of IEEE Inter. Symp. on Circuits and Systems (ISCAS), 1992
  • Direct Mapping of Nested Loops on Piecewise Regular Processor Arrays

    In Algorithms and Parallel VLSI Architectures, 1992
    • Dimitrios Soudris ,
    • P. Poechmueller ,
    • Efstathios Kyriakis-Bitzaros ,
    • Michael Birbas ,
    • Costas Goutis and
    • M. Glesner

    Design Methodology for Systematic Derivation of Fault-Tolerant Array Processors

    In Proc. IEEE Inter. Conf. on Computer Systems and Software Engineering, COMPEURO'92, 1992
  • Direct Mapping of Nested Loops and Efficient Decomposition of Uniform Rec urrences for Implementation on Array Architectures

    In Algorithms and Parallel VLSI Architectures, 1991
  • Design Methodology for Direct Mapping Iterative Algorithms on Array Architectures

    In Proc. of IEEE Inter. Symposium on Circuits and Systems (ISCAS), 1991
  • Design Methodology for Mapping Iterative Algorithms on Piecewise Regular Processor Arrays

    In Proc. of IEEE CompEuro '91, 1991
    • Dimitrios Soudris ,
    • Michael Birbas ,
    • Odysseas Koufopavlou ,
    • Dimitris Metafas ,
    • Spyridon Nikolaidis ,
    • Costas Goutis and
    • Sergios Theodoridis

    All-Digital Spectrum Analyzer Based on a Parallel Algorithm

    In Proc. of Melecon'91, 1991
  • A New Method for Mapping Iterative Algorithms on Regular Arrays

    In Proc. of IEEE Bilkent Inter. Conf. on New Trends on Communications, Control, and Signal Processing, 1990

    Workshops

  • Portable exploitation of parallel and heterogeneous HPC architectures in neural simulation using SkePU

    Proceedings of the 23rd International Workshop on Software and Compilers for Embedded Systems, SCOPES 2020, DOI: 10.1145/3378678.3391889
  • Interference-Aware Orchestration in Kubernetes

    Workshop on Virtualization in High-Performance Cloud Computing
      BibTeX
  • Towards plug&play smart thermostats inspired by reinforcement learning

    Workshop on INTelligent Embedded Systems Architectures and Applications
      BibTeX
  • A Comparative Evaluation of Xeon Phi Platforms Based on a Hodgkin-Huxley Neuron Simulator

    IXPUG 2017 Annual US Meeting, September 26-28, 2017, Austin, TX, USA
  • High Level Synthesis versus HDL: A Case study on Hardware Accelerators for Financial Appliacations

    in WRC: 11th HiPEAC Workshop on Reconfigurable Computing, Monday, Jan. 23, 10:00 - 17:30, Stockholm 2017
    • Dimitris Rodopoulos ,
    • Philippe Roussel ,
    • Francky Catthoor ,
    • Yiannakis Sazeides and
    • Dimitrios Soudris

    Approximating Standard Cell Delay Distributions by Reformulating the Most Probable Failure Point

    in W05 ERMAVSS: Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, Friday Workshop of DATE 2016, March 14-18, Dresden, Germany
  • HLS code transformation strategies and directives exploration for FPGA accelerated ECG analysis

    in 10th HiPEAC Workshop on Reconfigurable Computing, January 19th, 2016, Prague
  • A Real-Time, High-Performance FPGA Implementation of a Feed-Forward Equalizer for Optical Interconnects

    in 10th HiPEAC Workshop on Reconfigurable Computing, January 19th, 2016, Prague
  • Performance and Energy Consumption Evaluation of the Client-Server Synchronization Model for Concurrent Lists in Embedded Systems

    in Eight Workshop on Programmability Issues for Heterogeneous Multicores (MULTIPROG-2015), held in conjunction with the 10th International Conference on High- Performance and Embedded Architectures and Compilers (HiPEAC) Amsterdam, The Netherlands, January 20, 2015
  • A Genetic Algorithm Based Partitioning for 3-D Reconfigurable Architectures

    in 9th HiPEAC Workshop on Reconfigurable Computing 2015, WRC 2015, collocated with HiPEAC Conference 2015, Jan. 19-21, 2015, Amsterdam, The Netherlands
  • A Framework for Rapid System-Level Synthesis Targeting to Reconfigurable Platforms

    in 9th HiPEAC Workshop on Reconfigurable Computing 2015, WRC 2015, collocated with HiPEAC Conference 2015, Jan. 19-21, 2015, Amsterdam, The Netherlands
    • Ioannis Koutras ,
    • Patrick Bellasi ,
    • Alexandros Bartzas ,
    • William Fornaciari and
    • Dimitrios Soudris

    Extending Runtime Resource Management to Optimize Heap Memory Utilization of Embedded Applications

    in 2013 Design Automation Conference (DAC) Work-in-Progress Session, Austin, TX, June 2-6, 2013
    • Ioannis Koutras ,
    • Patrick Bellasi ,
    • Alexandros Bartzas ,
    • William Fornaciari and
    • Dimitrios Soudris

    Improving heap memory utilization of Embedded Applications via Run-Time Resource Management

    in DEPCP Friday Workshop,held in conjunction with the DATE 2013 Conference
    • Ioannis Koutras ,
    • Patrick Bellasi ,
    • Alexandros Bartzas ,
    • William Fornaciari and
    • Dimitrios Soudris

    A genetic algorithm- based FPGA placer for multi-core processors

    in DEPCP Friday Workshop,held in conjunction with the DATE 2013 Conference
  • A Reconfigurable Baseband Architecture for Gbps Wireless 60 GHz Communications

    in DEPCP Friday Workshop,held in conjunction with the DATE 2013 Conference
    • Alexandros Bartzas ,
    • Patrick Bellasi ,
    • J. Brandenburg ,
    • William Fornaciari ,
    • Ioannis Koutras ,
    • Giuseppe Massari ,
    • G. Palermo ,
    • Edoardo Paone ,
    • Cristina Silvano ,
    • Dimitrios Soudris ,
    • Sotirios Xydis and
    • V. Zaccaria

    Cooperative Design Space Exploration and Run-Time Resource Management for Application Adaptivity on Multi-Core Platforms: A Networked Video Surveillance Use Case

    DEPCP Friday Workshop,held in conjunction with the DATE 2013 Conference
  • A Framework for Performing Fault- Tolerant Placement Based on Genetic Algorithm

    in Workshop on Reconfigurable Computing (WRC), January 21, 2013, Co-located with HiPEAC Conference 2013, Berlin, Germany
  • SPARTAN: Efficient Implementation of Computer Vision Algorithms for Autonomous Rover Navigation

    in Workshop on Reconfigurable Computing (WRC), January 21, 2013, Co-located with HiPEAC Conference 2013, Berlin, Germany
  • An FPGA implementation of SURF algorithm for the ExoMars programme

    in Workshop on Reconfigurable Computing (WRC), January 21, 2013, Co-located with HiPEAC Conference 2013, Berlin, Germany
  • Advantages of High-Level Synthesis in an OpenCL Based FPGA Programming Methodology

    HLS4HPC Workshop, High-Level Synthesis for High Performance Computing, HiPEAC 2013, Berlin January 21-23, 2013
  • Thermal-aware SoC design through micro-architectures selective block replication

    in ACACES 2012, Eighth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 8-14 July, 2012, Fiuggi, Italy
  • A Design Space Exploration Prototype for Run-Time Support on Manycore Architectures

    Work-In-Progress Workshop, June 6, 2012, Design Automation Conference, San Francisco, USA
  • Adaptive Heap Management on Many-Core Platforms

    in DATE 2012 Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications (DEPCP 2012), Dresden, Germany, March 12-16, 2012
  • Towards Accelarating Computer Vision Algorithms Targeting to Space Applications with a Heterogeneous Platform

    in DATE 2012 Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications (DEPCP 2012), Dresden, Germany, March 12- 16, 2012
    • Patrick Bellasi ,
    • William Fornaciari ,
    • Giuseppe Massari ,
    • Cristina Silvano ,
    • Alexandros Bartzas and
    • Dimitrios Soudris

    Run-time Adaptivity Techniques – The 2PARMA Approach

    in DATE 2012 Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications (DEPCP 2012), Dresden, Germany, March 12-16, 2012
  • SYSMANTIC: A 3D NoC MPSoC Architecture Exploration and Implementation Framework

    Poster in DEPCP 2012, DATE Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, Dresden, Germany, March 12-16, 2012
  • Low-cost fault tolerant targeting FPGA devices

    in Proc. of WRC 2012, 6th HiPEAC Workshop on Reconfigurable Computing, January 24, 2012, Paris, France
  • NAROUTO: A Framework for exploration of 2D and 3D Heterogeneous FPGA Architecture

    ACACES 2011 Seventh International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 10-16 July, 2011, Fiuggi, Italy
    • Marcos Avilés Rodrigálvarez ,
    • Kostas Siozios ,
    • Dionisis Diamantopoulos ,
    • Lazaros Nalpantidis ,
    • I. Kostavelis ,
    • Evangelos Boukas ,
    • Dimitrios Soudris and
    • Antonios Gasteratos

    Workshop on Computer Vision on Low-Power Reconfigurable Architectures

    International Conference on Field Programmable Logic and Applications, Sept. 2011, Chania, Greece
  • Custom Microcoded Dynamic Memory Management for McNoC Platforms with Distributed Memories

    Poster in DEPCP 2011, DATE Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications
    • Cristina Silvano ,
    • William Fornaciari ,
    • D. Siorpaes ,
    • B. Stabernack ,
    • Chantal Ykman-Couvreur ,
    • Dimitrios Soudris ,
    • T. Kempf and
    • B. Vanthournout

    2PARMA: PARallel PAradigms and Runtime MAnagement techniques for Many-core Architectures

    Poster for DEPCP 2011, DATE Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications
  • Rapid Evaluation of 3-D Interconnection Schemes

    W5 3D Integration Workshop, DATE'11 Friday Workshop, Grenoble, France, March 14-18, 2011
  • Systematic Synthesis of Multimode Reconfigurable RTL Components

    in 5th HiPEAC Workshop on Reconfigurable Computing, WRC 2011, January 23, 2011, Heraklion, Crete
  • A Methodology and Tool Framework for Supporting Rapid Exploration of Memory Hierarchies in FPGAs

    in 5th HiPEAC Workshop on Reconfigurable Computing, WRC 2011, January 23, 2011, Heraklion, Crete
  • Microcoded Dynamic Memory Allocation for Multi-core Networks-on-Chip

    in ACACES 2010, 11-17 july, 2010, Terrassa, Barcelona, Spain
  • Dynamic Memory Management Customization for Multi-Processor Systems-on-Chip

  • A High-Level Tool Framework for Exploring and Designing NoC Architectures for 3D ICs

    in University Booth, DATE 2010, Dresden, Germany
  • A Novel NOC Architecture Framework for 3D Chip MPSoC Implementations

    in W5 3D Integration Workshop, DATE'10 Friday Workshop, March 8-12, 2010
  • Dynamic Memory Management Customization for Multi-Processor Systems-on-Chip

    Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, DATE'10 Friday Workshop, March 8-12, 2010
  • Design Tools Session: A Genetic Algorithm Framework for Dynamic Data Type Optimization and Memory Assignment

    in Workshop Designing for embedded parallel computing platforms: architectures, tools, and applications, Friday 24th April, Nice, France
  • Multi-granularity NoC simulation framework for early phase exploration of SDR platforms

    in Workshop Designing for embedded parallel computing platforms: architectures, tools, and applications, Friday 24th April, Nice, France
  • Reliability Breakdown Analysis of an MP-SoC platform due to Interconnect Wear-out

    in 2nd HiPEAC Workshop on Design for Reliability (DFR’10) January 24th, 2010 Pisa, ITALY
  • Fault-Free: A Framework for Supporting Fault Tolerance in FPGAs

    in Proc. of WRC 2010, 4th HiPEAC Workshop on Reconfigurable Computing, January 23, 2010, Pisa, Italy
  • 3D Networks-on-Chip: Architectures and tools

    in ACACES 2009, Barcelona, Spain
  • System-Level Exploration of 3-D Interconnection Schemes

    DATE'09 Friday Workshop on 3D Integration, Friday 24th April, Nice, France
  • Τopology Exploration and Buffer Sizing for Three- Dimensional Networks-on-Chip

    DATE'09 Friday Workshop on 3D Integration, Friday 24th April, Nice, France
  • A Novel Methodology for Exploring Interconnection Architectures Targeting 3-D FPGAs

    in 3rd HiPEAC Workshop on Reconfigurable Computing, January 25, 2009, Paphos, Cyprus

    Article

  • Seamless FPGA deployment over spark in cloud computing: A use case on machine learning hardware acceleration

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) DOI: 10.1007/978-3-319-78890-6_54
  • Efficient hardware acceleration of recommendation engines: A use case on collaborative filtering

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) DOI: 10.1007/978-3-319-78890-6_6