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Academics

Sotirios Xydis
   Assistant Professor
   (+30) 210-772-3653
   9 Heroon Polytechneiou, Zographou Campus 157 80 Athens - Greece

Sotirios Xydis is a Graduate in Electrical and Computer Engineering (2005) from the National Technical University of Athens. He received a Master’s Degree in Techno-Economic Systems in 2011 and a PhD from the School of Electrical and Computer Engineering of NTUA also in the same year. Between 2011-2013, he worked as a Post-doctoral Researcher at the Dipartimento di Elettronica, Informazione e Bioingegneria of the Politecnico di Milano, with conducting research on design space exploration and optimization techniques for heterogeneous multi-/many-core hardware architectures. Since 2014, he has been a collaborating researcher at the Institute of Communication and Computer Systems (ICCS). Between 2015-2018, he worked as an Engineer at the Operator of the Hellenic Electricity Distribution Network (HEDNO). Then, for the period 2020-2023, he served as an Assistant Professor in the Department of Informatics and Telematics at the Harokopion University of Athens. From February 2023 he is an Assistant Professor at the School of Electrical and Computer Engineering (Sector of Information and Computer Technology) of the National Technical University of Athens.

His research interests focus on hardware/software co-design of digital systems, heterogeneous system optimization techniques for low power and/or energy-efficient hardware accelerators, and memory and resource management in embedded and cloud computing systems. He has participated in more than 15 European and national research and development projects as a Researcher, Technical Coordinator and Principal Investigator.

Dr. Xydis’ research work includes more than 120 publications in international scientific journals, proceedings of international conferences and books, while his work has cited more than 1500 times according to Google Scholar. He is regularly a Reviewer or member of Program Committees at key conferences in his area such as DATE, FPL, ICCAD, DAC, ISCA, etc. His research work has been honored three times with the best scientific paper award at international scientific conferences, i.e. IEEE/NASA/ESA Adaptive Hardware Systems (AHS 2007), ACM Parallel Programming and Run-Time Management Techniques for Many-core Architectures (PARMA 2013) and ACM Computing Frontiers (CF 2020), while he has received a Hipeac award for his work at DAC’19 and DAC’20.

    Book Chapters

  • “Energy-efficient acceleration of Spark Machine Learning applications on FPGAs,” pp. 91-109, Book Chapter in Christoforos Kachris, Babak Falsafi and Dimitrios Soudris, “Hardware Accelerators in Data Centers”

    Springer Publishers, 2018. DOI: 10.1007/978-3-319-92792-3

  • “Software Design and Optimization of ECG Signal Analysis and Diagnosis for Embedded IoT Devices,” in Book “Components and Services for IoT Platforms: Paving the Way for IoT Standards”

    Editors Nikolaos Voros, Georgios Keramidas and Michael Hübner, Springer. DOI 10.1007/978-3-319- 42304-3_15
    • Cristina Silvano ,
    • William Fornaciari ,
    • S. Crespi Reghizzi ,
    • G. Agosta ,
    • G. Palermo ,
    • V. Zaccaria ,
    • Patrick Bellasi ,
    • F. Castro ,
    • Simone Corbetta ,
    • A. Di Biagio ,
    • E. Speziale ,
    • M. Tartara ,
    • D. Siorpaes ,
    • H. Hubert ,
    • B. Stabernack ,
    • J. Brandenburg ,
    • M. Palkovic ,
    • P. Raghavan ,
    • Chantal Ykman-Couvreur ,
    • Alexandros Bartzas ,
    • Sotirios Xydis ,
    • Dimitrios Soudris ,
    • T. Kempf ,
    • G. Ascheid ,
    • R. Leupers ,
    • H. Meyr ,
    • J. Ansari ,
    • P. Mahonen and
    • B. Vanthournout

    “2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures” Book Chapter in “VLSI 2010 Annual Symposium”

    Editors Lecture Notes in Electrical Engineering, Volume 57, pg. 65-79, 1st Edition., 2011, VIII, 331 p. Springer Netherlands, August 31, 2011, ISBN 978-94-007-1487-8
    • B. Candaele ,
    • S. Aguirre ,
    • M. Sarlotte ,
    • Iraklis Anagnostopoulos ,
    • Sotirios Xydis ,
    • Alexandros Bartzas ,
    • Dimitris Bekiaris ,
    • Dimitrios Soudris ,
    • Zhonghai Lu ,
    • Xiaowen Chen ,
    • J.M. Chabloz ,
    • A. Hemani ,
    • A. Jantsch ,
    • G. Vanmeerbeeck ,
    • J. Kreku ,
    • K. Tiensyrja ,
    • Fragkiskos Ieromnimon ,
    • D. Kritharidis ,
    • A. Wiefrink ,
    • B. Vanthournout and
    • P. Martin

    “The MOSART Mapping Optimization for multi-core ArchiTectures,” Book Chapter in “Designing Very Large Scale Integration Systems: Emerging Trends & Challenges”

    Editors: N. Voros, A. Mukherjee, N. Sklavos, K. Masselos, M. Huebner, Springer 2011

  • “A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning,” Book Chapter in “Designing Very Large Scale Integration Systems: Emerging Trends & Challenges”

    Editors: N. Voros, A. Mukherjee, N. Sklavos, K. Masselos, M. Huebner, Springer 2011
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    Conferences

  • BLonD++: Performance analysis and optimizations for enabling complex, accurate and fast beam dynamics studies

    ACM International Conference Proceeding Series DOI: 10.1145/3229631.3229640

  • TF2FPGA: A Framework for Projecting and Accelerating Tensorflow CNNs on FPGA Platforms

    2019 8th International Conference on Modern Circuits and Systems Technologies, MOCAST 2019, DOI: 10.1109/MOCAST.2019.8741940

  • Co-design Implications of Cost-effective On-demand Acceleration for Cloud Healthcare Analytics: The AEGLE approach

    Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019, DOI: 10.23919/DATE.2019.8714934

  • Cooperative arithmetic-aware approximation techniques for energy-efficient multipliers

    Proceedings - Design Automation Conference, 2019, DOI: 10.1145/3316781.3317793

  • Dataflow acceleration of smith-waterman with traceback for high throughput next generation sequencing

    Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019, DOI: 10.1109/FPL.2019.00021

  • Resource-Aware MapReduce Runtime for Multi/Many-core Architectures

    Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020, DOI: 10.23919/DATE48585.2020.9116281

  • Scale-out beam longitudinal dynamics simulations

    17th ACM International Conference on Computing Frontiers 2020, CF 2020 - Proceedings, DOI: 10.1145/3387902.3392616

  • DDOT: Data driven online tuning for energy efficient acceleration

    Proceedings - Design Automation Conference, 2020, DOI: 10.1109/DAC18072.2020.9218734

  • Exploration of GPU sharing policies under GEMM workloads

    in Proceedings of International Workshop on Software and Compilers for Embedded Systems (SCOPES) 2020

  • AEGLE’s Cloud Infrastructure for Resource Monitoring and Containerized Accelerated Analytics

    in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017 DOI: 10.1109/ISVLSI.2017.70

  • Dataflow Acceleration of scikit-learn Gaussian Process Regression

    in PARMA-DITAM 2017 Workshop, 8th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures - 6rd Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2017

  • Computation Offloading Management and Resource Allocation for Low-power IoT Edge Devices

    in IEEE World Forum on Internet of Things, 2016

  • Multi-Level Approximation for Inexact Accelerator Synthesis Under Voltage Island Constraints

    in Workshop on Approximate Computing, 2016

  • Distributed QoS Management for Internet of Things under Resource Constraints

    Internet of Things: A Holistic Perspective, IoT Day is part of CODES+ISSS, 2016

  • Energy Profile Analysis of Zynq-7000 Programmable SoC for Embedded Medical Processing: Case study on ECG Arrhythmia Detection

    in Proc. of 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2016

  • Performance-Power Exploration of Software-Defined Big Data Analytics: The AEGLE Cloud Backend

    in International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2016

  • ECG Signal Analysis and Arrhythmia Detection on IoT wearable medical devices

    in Proc. of 5th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2016

  • Deploying and Monitoring Hadoop MapReduce Analytics on Single-chip Cloud Computer

    PARMA-DITAM Workshop, 7th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures – 5th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2016

  • High-Level Synthesis Extensions for Scalable Single-Chip Many-Accelerators on FPGAs

    in PhD Forum, International Conference on Field-programmable Logic and Applications (FPL), 2015

  • Rapid Prototyping and Design Space Exploration Methodologies for Many-Accelerator Systems

    PhD Forum, International Conference on Field-programmable Logic and Applications (FPL), 2015

  • Effective Learning and Filtering of Faulty Heart-Beats for Advanced ECG Arrhythmia Detection using MIT-BIH Database

    in Procedings of 5th International Conference on Wireless Mobile Communication and Healthcare (MOBIHEALTH), 2015

  • Job-Arrival Aware Distributed Run-Time Resource Management on Intel SCC Manycore Platform

    in Proceedings of 13th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC), 2015
    • Dimitrios Soudris ,
    • Sotirios Xydis ,
    • Christos Baloukas ,
    • Anastasia Hadzidimitriou ,
    • Ioanna Chouvarda ,
    • Kostas Stamatopoulos ,
    • Nicos Maglaveras ,
    • John Chang ,
    • Andreas Raptopoulos ,
    • David Manset ,
    • Barbara Pierscionek ,
    • Reem Kayyali ,
    • Nada Phillip ,
    • Tobias Becker ,
    • Katerina Vaporidi ,
    • Eumorphia Kondili ,
    • Dimitrios Georgopoulos ,
    • Lesley-Ann Sutton ,
    • Richard Rosenquist ,
    • Lydia Scarfo and
    • Paolo Ghia

    AEGLE: A Big Bio-Data Analytics Framework for Integrated Health-Care Services

    in Proceedings of International Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), 2015

  • Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach

    in Proceedings of the 11th International Symposium on Applied Reconfigurable Computing (ARC), 2015

  • SWAN-iCARE project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring

    in Proceedings of the 11th International Symposium on Applied Reconfigurable Computing (ARC), 2015

  • Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures

    in Proceedings of the 11th International Symposium on Applied Reconfigurable Computing (ARC), 2015

  • A HW/SW Framework Emulating Wearable Devices For Remote Wound Monitoring and Management

    in Proceedings of 4th International Conference on Wireless Mobile Communication and Healthcare (MOBIHEALTH), 2014

  • Hardware Accelerated Rician Denoise Algorithm for High Performance Magnetic Resonance Imaging

    in 4th International Conference on Wireless Mobile Communication and Healthcare (MOBIHEALTH), 2014

  • Effective Platform-Level Exploration for Heterogeneous Multicores Exploiting SimulationInduced Slacks

    in PARMA-DITAM 2014 Workshop, 5th Workshop on Parallel Programming and RunTime Management Techniques for Many-core Architectures - 3rd Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2014

  • A Framework for Supporting Parallel Application Placement onto Reconfigurable Platforms

    in Proceedings of PARMA Workshop, 2013

  • Thermal optimization for micro-architectures through selective block replication

    in Proceedings of Int. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), 2011

  • Runtime Tuning of Dynamic Memory Management For Mitigating Footprint-Fragmentation Variations

    in Proceedings of 2nd PARMA Workshop on Parallel Programming and Run-Time Management Techniques for Manycore Architectures, 2011

  • Custom Multi-Threaded Dynamic Memory Management for Multiprocessor System-on-Chip Platforms

    in Proceedings - 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2010

  • High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures

    in Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2010
    • Cristina Silvano ,
    • William Fornaciari ,
    • S. Crespi Reghizzi ,
    • G. Agosta ,
    • G. Palermo ,
    • V. Zaccaria ,
    • F. Castro ,
    • Simone Corbetta ,
    • A. Di Biagio ,
    • E. Speziale ,
    • M. Tartara ,
    • D. Siorpaes ,
    • H. Hubert ,
    • B. Stabernack ,
    • J. Brandenburg ,
    • M. Palkovic ,
    • P. Raghavan ,
    • Chantal Ykman-Couvreur ,
    • Alexandros Bartzas ,
    • Sotirios Xydis ,
    • Dimitrios Soudris ,
    • T. Kempf ,
    • G. Ascheid ,
    • R. Leupers ,
    • H. Meyr ,
    • J. Ansari ,
    • P. Mahonen and
    • B. Vanthournout

    2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures

    in Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2010
    • B. Candaele ,
    • S. Aguirre ,
    • M. Sarlotte ,
    • Iraklis Anagnostopoulos ,
    • Sotirios Xydis ,
    • Alexandros Bartzas ,
    • Dimitris Bekiaris ,
    • Dimitrios Soudris ,
    • Zhonghai Lu ,
    • Xiaowen Chen ,
    • J.M. Chabloz ,
    • A. Hemani ,
    • A. Jantsch ,
    • G. Vanmeerbeeck ,
    • J. Kreku ,
    • K. Tiensyrja ,
    • Fragkiskos Ieromnimon ,
    • D. Kritharidis ,
    • A. Wiefrink ,
    • B. Vanthournout and
    • P. Martin

    Mapping Optimisation for Scalable multi-core ARchiTecture: The MOSART approach

    in Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2010

  • Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching

    in Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2010

  • Designing Efficient DSP Datapaths Through Compiler-in-the-Loop Exploration Methodology

    in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), 2010

  • Construction of Dual Mode Components for Reconfiguration Aware High-Level Synthesis

    in Design Automation and Test in Europe (DATE), 2010

  • Joint Exploitation of Horizontal/Vertical Parallelism and Operation Chaining for Flexible DSP Synthesis

    in IFIP/IEEE International Conference on VLSI -SOC, 2008

  • Mapping DSP Applications onto HighPerformance Architectural Templates with Inlined Flexibility

    in Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2008
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    Workshops

  • Interference-Aware Orchestration in Kubernetes

    Workshop on Virtualization in High-Performance Cloud Computing
      BibTeX
    @inproceedings{tzenetopoulos2020interference, title={Interference-Aware Orchestration in Kubernetes}, author={Tzenetopoulos, Achilleas and Masouros, Dimosthenis and Xydis, Sotirios and Soudris, Dimitrios}, booktitle={International Conference on High Performance Computing}, pages={321--330}, year={2020}, organization={Springer} }

  • HLS code transformation strategies and directives exploration for FPGA accelerated ECG analysis

    in 10th HiPEAC Workshop on Reconfigurable Computing, January 19th, 2016, Prague
    • Alexandros Bartzas ,
    • Patrick Bellasi ,
    • J. Brandenburg ,
    • William Fornaciari ,
    • Ioannis Koutras ,
    • Giuseppe Massari ,
    • G. Palermo ,
    • Edoardo Paone ,
    • Cristina Silvano ,
    • Dimitrios Soudris ,
    • Sotirios Xydis and
    • V. Zaccaria

    Cooperative Design Space Exploration and Run-Time Resource Management for Application Adaptivity on Multi-Core Platforms: A Networked Video Surveillance Use Case

    DEPCP Friday Workshop,held in conjunction with the DATE 2013 Conference

  • Thermal-aware SoC design through micro-architectures selective block replication

    in ACACES 2012, Eighth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 8-14 July, 2012, Fiuggi, Italy

  • A Design Space Exploration Prototype for Run-Time Support on Manycore Architectures

    Work-In-Progress Workshop, June 6, 2012, Design Automation Conference, San Francisco, USA

  • Custom Microcoded Dynamic Memory Management for McNoC Platforms with Distributed Memories

    Poster in DEPCP 2011, DATE Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications

  • Microcoded Dynamic Memory Allocation for Multi-core Networks-on-Chip

    in ACACES 2010, 11-17 july, 2010, Terrassa, Barcelona, Spain

  • Dynamic Memory Management Customization for Multi-Processor Systems-on-Chip

  • Dynamic Memory Management Customization for Multi-Processor Systems-on-Chip

    Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, DATE'10 Friday Workshop, March 8-12, 2010
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