Academics

Kostas Siozios
  
   Aristotle University of Thessaloniki (AUTH), Thessaloniki, 54124, Greece.

Kostas Siozios received his Diploma, Master and Ph.D. Degree in Electrical and Computer Engineering from the Democritus University of Thrace, Greece, in 2001, 2003 and 2009, respectively. Currently he is Assistant Professor at Department of Physics, Aristotle University of Thessaloniki, Greece. His research interests include system orchestrators, CAD algorithms, reconfigurable architectures, many-accelerator architectures, 3-D integration and network-on-chip. He has published more than 140 papers in international journals and conferences. Also, he has co-editor/co-author in 10 books of Springer, CRC Press
and River Publishers. He is IEEE member for 10 years. The last years he works as principal investigator in numerous research projects funded from the European Commission (EC), European Space Agency (ESA), as well as the Greek Government and Industry.

    Book Chapters

  • Towards Plug&Play Smart Thermostats for Building’s Heating/Cooling Control

    In: Siozios K., Anagnostos D., Soudris D., Kosmatopoulos E. (eds) IoT for Smart Grids. Power Systems. Springer, Cham
      BibTeX
  • “On Designing Decision-Making Mechanisms for Cyber-Physical Systems” in Book “Cyber-Physical Systems: Decision Making Mechanisms and Applications”

    River Publishers. 2017
  • “PReDiCt: A Scenario-based Methodology for Realizing Decision-Making Mechanisms Targeting Cyber-Physical Systems” in Book “Cyber-Physical Systems: Decision Making Mechanisms and Applications”

    River Publishers. 2017
  • “Supporting Decision Making for Large-Scale IoTs: Trading Accuracy with Computational Complexity”, in Book “Components and Services for IoT Platforms: Paving the Way for IoT Standards”

    Editors Nikolaos Voros, Georgios Keramidas and Michael Hübner, Springer, 2017
  • “Architectures and CAD Tools for 3D FPGAs,” in Book “Reconfigurable Logic: Architecture, Tools and Applications,”

    CRC Press, 2015
  • “A Temperature-Aware Placement and Routing Algorithm Targeting 3D FPGAs”, Book Chapter in “VLSI-SOC: Design Methodologies for SoC and SiP,”

    Piguet, R. Reis, and D. Soudris (Eds.): VLSI-SoC 2008, IFIP AICT 313, pp. 251–270, Springer, Dordrecht/London/Boston, Feb. 2010
  • “Three Dimensional Network-on-Chip Architectures,” Chapter 2, in “Networks-on-Chips: Theory and practice”

    CRC Press, 2008
    • Dimitrios Soudris ,
    • Konstantinos Tatas ,
    • Kostas Siozios ,
    • G. Koutroumpezis ,
    • Spyridon Nikolaidis ,
    • Stylianos Siskos ,
    • N. Vasiliadis ,
    • V. Kalenteridis ,
    • H. Pournara and
    • I. Pappas

    “AMDREL: A Novel Low-Energy FPGA Architecture and Supporting CAD Tool Design Flow”, Chapter 3 in “Fine and Coarse-Grain Reconfigurable Systems”

    Editors: S. Vassiliadis and D. Soudris, Springer, 2007
  • “Survey of Fine-Grain Reconfigurable Architectures and Processors”, Chapter 1 in “Fine- and Coarse-Grain Reconfigurable Systems”

    Editors: S. Vassiliadis and D. Soudris, Springer, 2007

    Journals

  • OpenCL-based virtual prototyping and simulation of many-accelerator architectures

    ACM Transactions on Embedded Computing Systems
  • Rapid Prototyping of Low-Complexity Orchestrator Targeting CyberPhysical Systems: The Smart-Thermostat Usecase

    IEEE Transactions on Control Systems Technology
      BibTeX
  • A Flexible Decision-Making Mechanism Targeting Smart Thermostats

    IEEE Embedded Systems Letters, 9 (4), 2017
  • On Supporting Rapid Prototyping of Embedded Systems with Reconfigurable Architectures

    Integration, the VLSI Journal, 58 (2017)
  • A Low-Complexity Control Mechanism Targeting Smart Thermostats

    Energy and Buildings, Elsevier, 139 (2017)
  • A Framework for Interconnection-Aware Domain-Specific Many-Accelerator Synthesis

    ACM Transactions on Embedded Computing Systems (TECS), Volume 16 Issue 1, November 2016
  • ANT3D: Simultaneous Partitioning and Placement for 3-D FPGAs based on Ant Colony Optimization

    IEEE Embedded Systems Letters, 2016
  • A Customizable Framework for Application Implementation onto 3-D FPGAs

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.: 35, Issue: 11, Nov. 2016
  • An Integrated Exploration and Virtual Platform Framework for Many-Accelerator Heterogeneous Systems

    ACM Transactions on Embedded Computing Systems (TECS), Volume 15 Issue 3, July 2016
  • An Evolutionary Algorithm for Netlist Partitioning Targeting 3-D FPGAs

    IEEE Embedded Systems Letters, Volume:7, Issue: 4, December 2015
  • Mitigating Memoryinduced Dark Silicon in Many-Accelerator Architectures

    IEEE Computer Architecture Letters, Vol.: 14, Issue: 2, March 2015
  • GENESIS: Parallel Application Placement onto Reconfigurable Architectures

    ACM TECS, Trans. Embedded Computing Systems, Vol. 14, No. 1, Article 18, January 2015
  • Plug&Chip: A Framework for Supporting Rapid Prototyping of 3-D Hybrid Virtual SoCs

    ACM Transactions on Embedded Computing Systems (TECS), Vol. 13, No. 5s, Article 168, November 2014
  • A Framework for Supporting Adaptive Fault Tolerant Solutions

    ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Risk and Trust in Embedded Critical Systems, Special Issue on Real-Time, Embedded and CyberPhysical Systems, Special Issue on Virtual Prototyping of Parallel and Embedded Systems (ViPES), Volume 13 Issue 5s, November 2014
  • A Novel 3-D FPGA Architecture Targeting Communication Intensive Applications

    Journal of Systems Architecture, Volume 60, Issue 1,January 2014
  • SPARTAN: Developing a Vision System for Future Autonomous Space Exploration Robots

    Journal of Field Robotics, Special Issue: Special Issue on Space Robotics, Part 2, Volume 31, Issue 1, pages 107– 140, January/February 2014
  • A low-cost fault tolerant solution targeting commercial FPGA devices

    Journal of Systems Architecture, 59 (2013)
  • A Framework for Rapid Evaluation of Heterogeneous 3-D NoC Architectures

    Microprocessors and Microsystems, Elsevier. October 2013
  • JITPR: A Framework for Supporting Fast Application’s Implementation onto FPGAs (RAW 2012 special issue)

    ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012), Volume 6, Issue 2, July 2013
  • On Supporting Rapid Exploration of Memory Hierarchies onto FPGAs

    Journal of Systems Architecture, Journal of Systems Architecture 59 (2013)
  • A Framework for Performing Rapid Evaluation of 3-D SoCs

    Electronics Letters, Volume: 48, Issue: 12, pp. 679 – 681, 7 June 2012
  • A Systematic Methodology for Reliability Improvements on SoC-based Software Defined Radio Systems

    VLSI Design, Volume 2012
  • A Novel Framework for Exploring 3-D FPGAs with Heterogeneous Interconnect Fabric

    in ACM Transactions on Reconfigurable Technology and Systems, Vol. 5, Issue 1, March 2012
  • A Tabu-based Partitioning Algorithm Targeting to 3-D FPGAs

    IEEE Embedded Systems Letters, Vol. 3, No. 3, September 2011
  • On Supporting Rapid Thermal Analysis

    IEEE Computer Architecture Letters, Issue Date: July-Dec. 2011
  • A Methodology for Alleviating the Performance Degradation of TMR Solutions

    IEEE Embedded Systems Letters, Volume 2, Issue 4, December 2010
  • A Novel Allocation Methodology for Partial and Dynamic Bitstream Generation of FPGA Architectures

    Journal of Circuits, Systems, and Computers, JCSC, Vol. 19, No. 3 (2010)
  • Designing a Novel High-Performance FPGA Architecture for Data Intensive Applications

    Journal of Real-Time Image Processing, (2009)
  • A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs

    JOLPE - Journal of Low Power Electronics, Vol. 4, Νο. 3, pp. 275–289, 2008
  • Architecture-Level Exploration of Alternative Interconnection Schemes Targeting to 3D FPGAs: A Software-Supported Methodology

    International Journal of Reconfigurable Computing, Volume 2008 (2008)
  • Designing a General-Purpose Interconnection Architecture for FPGAs

    JOLPE - Journal of Low Power Electronics, 4, 34-47 (2008)
    • Kostas Siozios ,
    • G. Koutroumpezis ,
    • Konstantinos Tatas ,
    • N. Vasiliadis ,
    • V. Kalenteridis ,
    • H. Pournara ,
    • I. Pappas ,
    • Dimitrios Soudris ,
    • Adonios Thanailakis ,
    • Spyridon Nikolaidis and
    • Stylianos Siskos

    A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications

    IEICE Transactions on Information and Systems, "Special Issue on Recent Advances in Circuits and Systems", vol. E88-D, No. 7 July 2005
    • V. Kalenteridis ,
    • H. Pournara ,
    • Kostas Siozios ,
    • N. Vasiliadis ,
    • Konstantinos Tatas ,
    • I. Pappas ,
    • G. Koutroumpezis ,
    • Spyridon Nikolaidis ,
    • Stylianos Siskos ,
    • Dimitrios Soudris and
    • Adonios Thanailakis

    A Complete Platform and Toolset for System Implementation on Fine-Grain Reconfigurable Hardware

    Microprocessors and Microsystems, Special Issue on Field-Programmable Gate Arrays (FPGAs): Applications, Algorithms and Tools, Elsevier Publishers, 29 (2005)

    Conferences

  • From edge to cloud: Design and implementation of a healthcare internet of things infrastructure

    2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2017
  • Algorithmic and memory optimizations on multiple application mapping onto FPGAs

    in International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2017
  • FabSpace 2.0: A Platform for Application and Service Development based on Earth Observation Data

    in The International Conference on Modern Circuits and Systems Technologies (MOCAST), 2017
  • Parameter Sensitivity in Virtual FPGA Architectures

    in 13th International Symposium on Applied Reconfigurable Computing (ARC), 2017
  • Application Performance Improvement By Exploiting Process Variability On FPGA Devices

    in Proc. 20th Design Automation & Testing Exhibition (DATE), 2017
  • An OpenCL-based Framework for Rapid Virtual Prototyping of Heterogeneous Architectures

    in 4th Workshop on Virtual Prototyping of Parallel and Embedded Systems (VIPES), 2016
  • A Framework for Exploring Alternative Fault-Tolerant Schemes Targeting 3-D Reconfigurable Architectures

    in 4th Workshop on Virtual Prototyping of Parallel and Embedded Systems, co-located with the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2016
  • Parallel Application Placement onto 3-D Reconfigurable Architectures

    in Proc. of 5th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2016
    • Efstathios Sotiriou-Xanthopoulos ,
    • G. Shalina ,
    • Peter Figuli ,
    • Kostas Siozios ,
    • George Economakos and
    • Jurgen Becker

    A Power Estimation Technique for Cycle-Accurate Higher-Abstraction SystemC-based CPU Models

    In International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, 2015
  • High-Level Synthesis Extensions for Scalable Single-Chip Many-Accelerators on FPGAs

    in PhD Forum, International Conference on Field-programmable Logic and Applications (FPL), 2015
  • Rapid Prototyping and Design Space Exploration Methodologies for Many-Accelerator Systems

    PhD Forum, International Conference on Field-programmable Logic and Applications (FPL), 2015
  • SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms

    in Proceedings of the 11th International Symposium on Applied Reconfigurable Computing (ARC), 2015
  • A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware

    in Proceedings of the 11th International Symposium on Applied Reconfigurable Computing (ARC), 2015
  • Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures

    in Proceedings of the 11th International Symposium on Applied Reconfigurable Computing (ARC), 2015
  • TEAChER: TEach AdvanCEd Recongurable architectures and tools

    in Proceedings of the 11th International Symposium on Applied Reconfigurable Computing (ARC), 2015
  • Hardware Accelerated Rician Denoise Algorithm for High Performance Magnetic Resonance Imaging

    in 4th International Conference on Wireless Mobile Communication and Healthcare (MOBIHEALTH), 2014
  • A Framework for Customizing Virtual 3-D Reconfigurable Platforms at Run-Time

    in Proceedings of 21st Reconfigurable Architectures Workshop (RAW), 2014
  • Framework for Mapping Dynamic Virtual Kernels onto Heterogeneous Reconfigurable Platforms

    in Proceedings of 21st Reconfigurable Architectures Workshop (RAW), 2014
  • Effective Platform-Level Exploration for Heterogeneous Multicores Exploiting SimulationInduced Slacks

    in PARMA-DITAM 2014 Workshop, 5th Workshop on Parallel Programming and RunTime Management Techniques for Many-core Architectures - 3rd Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2014
  • A Platform-Independent Runtime Methodology For Mapping Multiple Applications Onto Fpgas Through Resource Virtualization

    in 23rd International Conference on Field Programmable Logic and Applications (FPL), 2013
  • A Process-Based Reconfigurable SystemC Module for Simulation Speedup

    in Proc. of 13th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2013
  • On Supporting Adaptive Fault Tolerant at Run-Time with Virtual FPGAs

    in Proceedings of the Workshop on Virtual Prototyping of Parallel and Embedded Systems (ViPES), 2013
  • HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips

    in Proceedings of the Workshop on Virtual Prototyping of Parallel and Embedded Systems (ViPES),2013
  • A Framework for Supporting Parallel Application Placement onto Reconfigurable Platforms

    in Proceedings of PARMA Workshop, 2013
  • FPGA-based Path-planning of High Mobility Rover for Future Planetary Missions

    in Proc. 19th IEEE International Conference on Electronics, Circuits, and Systems, 2012
  • On Designing Self-Aware Reconfigurable Platforms

    in Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012
  • Hardware Implementation of Stereo Correspondence Algorithm for the Exomars Mission

    in Proccedings of Field Programmable Logic (FPL), 2012
  • SPARTAN Project: On Profiling Computer Vision Algorithms for Rover Navigation

    in Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2012
  • A low-cost fault tolerant solution targeting to commercial FPGA devices

    in Special Session “Dependability by reconfigurable hardware” in Proc. of NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2012
  • On Supporting Efficient Partial Reconfiguration with Just-In-Time Compilation

    in Proceedings of RAW 9th Reconfigurable Architectures Workshop, 2012
  • “The SPARTAN Project: FPGA-based Implementation of Computer Vision Algorithms Targeting to Space Applications”

    PAnhellenic Conference on Electronics and Telecommunications (PACET), 2011, Greece
  • A Framework for Architecture-Level Exploration of 3-D FPGA Platforms

    in Proc. of 21th International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS), 2011
  • SPARTAN Project: Efficient Implementation of Computer Vision Algorithms onto Reconfigurable Platform Targeting to Space Applications

    in Proceedings of 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2011
  • A Methodology and Tool Framework For Supporting Rapid Exploration Of Memory Hierarchies In FPGAs

    in Proceedings of 21st International Conference on Field Programmable Logic and Applications (FPL), 2011
  • A Framework For Architecture-Level Exploration οf Communication Intensive Applications Onto 3-D FPGAs

    in Proceedings of 21st International Conference on Field Programmable Logic and Applications (FPL), 2011
  • Thermal optimization for micro-architectures through selective block replication

    in Proceedings of Int. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), 2011
  • Quick_Hotspot: A Software Supported Methodology for Supporting Run-Time Thermal Analysis at MPSoC Designs

    in Proceedings of 2nd PARMA Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures, 2011
  • Trading Fault-Masking with Performance Overhead for FPGAs

    in Proceedings of 1st Workshop on Software-Controlled, Adaptive Fault-Tolerance in Microprocessors (SCAFT), 2011
  • A Novel Methodology for Architecture-Level Exploration of 3D SoCs

    in Proceedings of 6th International conference on Design & Technology of Integrated Systems in nanoscale era (DTIS), 2011
  • CAD Tools for Designing 3D Integrated Systems

    in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), 2011
  • NAROUTO: An Open-Source Framework For Supporting Architecture-Level Exploration at Heterogeneous FPGAS

    in Proc. of 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2010
  • Multiple Vdd on 3D NoC Architectures

    in Proc. of 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2010
  • A High-Level Mapping Algorithm Targeting 3D NoC Architectures with Multiple Vdd

    in Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2010
  • Towards supporting Fault-Tolerance in FPGAs

    in Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2010
  • Fast Design Space Exploration Environment Applied on NoC’s for 3D-Stacked MPSoC’s

    in Proceedings of PARMA Workshop Parallel Programming and Run-time Management Techniques for Many-core Architectures, 2010
  • A Framework for Enabling Fault Tolerance in Reconfigurable Architectures

    in Proc. of 6th International Symposium on Applied Reconfigurable Computing (ARC), 2010
  • Three dimensional FPGA Architectures: A Shift Paradigm for Energy performance efficient DSP implemenentations

    in Proc. of 16th International Conference on Digital Signal Processing (DSP), 2009
  • A Software-Supported Methodology for Exploring Interconnection Architectures Targeting 3-D FPGAs

    in Proceedings of Design Automation Conference in Europe (DATE), 2009
  • A method and tool for early design/technology search-space exploration for 3D ICs

    in IFIP/IEEE International Conference on VLSI -SOC, 2008
  • A Novel Algorithm for Temperature-Aware P&R on 3D FPGAs

    in IFIP/IEEE International Conference on VLSI -SOC, 2008
  • An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs

    in Proceedings of International Workshop on Power and Timing, Modeling, Optimization and Simulation (PATMOS), 2008
  • MEANDER: A CAD Tool Framework for Designing 2D/3D FPGAs

    Third International Conference “Micro&Nano2007” on Micro-Nanoelectronics, Nanotechnology and MEMs, NCSR Demokritos, Athens, 18 – 21 November 2007
  • Application-domain-specific Reconfigurable FPGA Platform: An Integrated Hardware and Software Design Approach

    in Ph.D. Forum, Proc. of VLSI-SOC, IFIP Int. Conference on Very Large Scale Integration, 2007
  • Exploration of Alternative Topologies for Application Specific 3D Networks on Chip

    in Proceedings of Workshop on Application Specific Processors (WASP), 2007
  • A Software-Supported Methodology for Desinging High-Performance 3D FPGA Architectures

    in Proc. of VLSI-SOC, IFIP Int. Conference on Very Large Scale Integration, 2007
  • Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support

    in Proc. of FPL 2007, 17th Int. Conference on Field Programmable Logic and Applications, 2007
  • A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs

    in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2007
  • Designing Heterogeneous FPGAs with Multiple SBs

    International Workshop on Applied Reconfigurable Computing (ARC), 2007
  • A Temperature-Aware Mapping Methodology for FPGAs

    in Proc. of Fifteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2007
  • Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources

    in 16th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2006
  • Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique

    in Proc. Of IFIP International Conference on VLSI –VLSISOC, 2006
  • Wire segment length and switch box co-optimization for FPGA architectures

    in Proc. of 15th Int. Conference on Field Programmable Logic and Applications (FPL), 2006
  • A Novel Methodology for Designing High-Performance and Low-Power FPGA Interconnection Targeting DSP Applications

    in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), 2006
  • Platform-based FPGA Architecture: Designing High-Performance and Low-Power Routing Structure for Realizing DSP Applications

    in Proc. of RAW 2006, 13th Reconfigurable Architectures Workshop, 2006
  • A Novel Methodology for Designing HighPerformance and Low-Energy FPGA Routing Architecture

    in Proc. of Fourteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2006
    • Kostas Siozios ,
    • G. Koutroumpezis ,
    • Konstantinos Tatas ,
    • N. Vassiliadis ,
    • V. Kalenteridis ,
    • H. Pournara ,
    • I. Pappas ,
    • Dimitrios Soudris ,
    • Spyridon Nikolaidis ,
    • Stylianos Siskos and
    • Adonios Thanailakis

    The AMDREL Project in Retrospective

    in Proc. IFIP Inter. Conference in Very Large Scale Integration VLSI-SOC, 2005
  • A Low-Energy FPGA: Architecture Design and SoftwareSupported Design Flow

    in Proceedings of 14th Inter. Conference on Field Programmable Logic and Applications (FPL), 2005
  • An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform

    in Proceedings of 14th Inter. Conference on Field Programmable Logic and Applications (FPL), 2005
  • DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and its Software Tool Implementation

    in Proceedings of RAW 2005, 12th Reconfigurable Architectures Workshop, 2005
    • Dimitrios Soudris ,
    • Spyridon Nikolaidis ,
    • Stylianos Siskos ,
    • Konstantinos Tatas ,
    • Kostas Siozios ,
    • G. Koutroumpezis ,
    • N. Vasiliadis ,
    • V. Kalenteridis ,
    • H. Pournara ,
    • I. Pappas and
    • Adonios Thanailakis

    AMDREL: A Novel Low-Energy FPGA Architecture and Supporting CAD Tool Design Flow

    in Proc. of ASP-DAC 2005, Asia South Pacific – Design Automation Conference (Design Contest), 2005
    • I. Pappas ,
    • N. Vassiliadis ,
    • V. Kalenteridis ,
    • H. Pournara ,
    • Spyridon Nikolaidis ,
    • Stylianos Siskos ,
    • Kostas Siozios ,
    • G. Koutroumpezis ,
    • Konstantinos Tatas ,
    • Dimitrios Soudris and
    • Adonios Thanailakis

    Fine-Grain Reconfigurable Platform: FPGA Hardware Design and Software Toolset Development

    Proceedings of Microelectronics Microsystems and Nanotechnology, 14-17 November 2004, Greece
  • A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development

    in Proceedings of 13th International Conference on Field Programmable Logic and Applications (FPL), 2004
    • V. Kalenteridis ,
    • H. Pournara ,
    • Kostas Siozios ,
    • Konstantinos Tatas ,
    • I. Pappas ,
    • N. Vassiliadis ,
    • G. Koutroumpezis ,
    • Spyridon Nikolaidis ,
    • Stylianos Siskos ,
    • Dimitrios Soudris and
    • Adonios Thanailakis

    An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development

    in Proceedings of 11th Reconfigurable Architectures Workshop (RAW) , 2004
  • FPGA Architecture Design and Toolset for Logic Implementation

    in 13th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2003
  • Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms

    in 13th International Conference on Field Programmable Logic and Applications, 2003
  • Power Optimization Methodology for Multimedia Applications Implementation on Reconfigurable Platforms

    in 13th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2003

    Workshops

  • Towards plug&play smart thermostats inspired by reinforcement learning

    Workshop on INTelligent Embedded Systems Architectures and Applications
      BibTeX
  • A Genetic Algorithm Based Partitioning for 3-D Reconfigurable Architectures

    in 9th HiPEAC Workshop on Reconfigurable Computing 2015, WRC 2015, collocated with HiPEAC Conference 2015, Jan. 19-21, 2015, Amsterdam, The Netherlands
  • A Framework for Rapid System-Level Synthesis Targeting to Reconfigurable Platforms

    in 9th HiPEAC Workshop on Reconfigurable Computing 2015, WRC 2015, collocated with HiPEAC Conference 2015, Jan. 19-21, 2015, Amsterdam, The Netherlands
  • A Framework for Performing Fault- Tolerant Placement Based on Genetic Algorithm

    in Workshop on Reconfigurable Computing (WRC), January 21, 2013, Co-located with HiPEAC Conference 2013, Berlin, Germany
  • SPARTAN: Efficient Implementation of Computer Vision Algorithms for Autonomous Rover Navigation

    in Workshop on Reconfigurable Computing (WRC), January 21, 2013, Co-located with HiPEAC Conference 2013, Berlin, Germany
  • An FPGA implementation of SURF algorithm for the ExoMars programme

    in Workshop on Reconfigurable Computing (WRC), January 21, 2013, Co-located with HiPEAC Conference 2013, Berlin, Germany
  • Thermal-aware SoC design through micro-architectures selective block replication

    in ACACES 2012, Eighth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 8-14 July, 2012, Fiuggi, Italy
  • Towards Accelarating Computer Vision Algorithms Targeting to Space Applications with a Heterogeneous Platform

    in DATE 2012 Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications (DEPCP 2012), Dresden, Germany, March 12- 16, 2012
  • SYSMANTIC: A 3D NoC MPSoC Architecture Exploration and Implementation Framework

    Poster in DEPCP 2012, DATE Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, Dresden, Germany, March 12-16, 2012
  • Low-cost fault tolerant targeting FPGA devices

    in Proc. of WRC 2012, 6th HiPEAC Workshop on Reconfigurable Computing, January 24, 2012, Paris, France
  • NAROUTO: A Framework for exploration of 2D and 3D Heterogeneous FPGA Architecture

    ACACES 2011 Seventh International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 10-16 July, 2011, Fiuggi, Italy
    • Marcos Avilés Rodrigálvarez ,
    • Kostas Siozios ,
    • Dionisis Diamantopoulos ,
    • Lazaros Nalpantidis ,
    • I. Kostavelis ,
    • Evangelos Boukas ,
    • Dimitrios Soudris and
    • Antonios Gasteratos

    Workshop on Computer Vision on Low-Power Reconfigurable Architectures

    International Conference on Field Programmable Logic and Applications, Sept. 2011, Chania, Greece
  • Rapid Evaluation of 3-D Interconnection Schemes

    W5 3D Integration Workshop, DATE'11 Friday Workshop, Grenoble, France, March 14-18, 2011
  • Systematic Synthesis of Multimode Reconfigurable RTL Components

    in 5th HiPEAC Workshop on Reconfigurable Computing, WRC 2011, January 23, 2011, Heraklion, Crete
  • A Methodology and Tool Framework for Supporting Rapid Exploration of Memory Hierarchies in FPGAs

    in 5th HiPEAC Workshop on Reconfigurable Computing, WRC 2011, January 23, 2011, Heraklion, Crete
  • A High-Level Tool Framework for Exploring and Designing NoC Architectures for 3D ICs

    in University Booth, DATE 2010, Dresden, Germany
  • A Novel NOC Architecture Framework for 3D Chip MPSoC Implementations

    in W5 3D Integration Workshop, DATE'10 Friday Workshop, March 8-12, 2010
  • Fault-Free: A Framework for Supporting Fault Tolerance in FPGAs

    in Proc. of WRC 2010, 4th HiPEAC Workshop on Reconfigurable Computing, January 23, 2010, Pisa, Italy
  • 3D Networks-on-Chip: Architectures and tools

    in ACACES 2009, Barcelona, Spain
  • System-Level Exploration of 3-D Interconnection Schemes

    DATE'09 Friday Workshop on 3D Integration, Friday 24th April, Nice, France
  • Τopology Exploration and Buffer Sizing for Three- Dimensional Networks-on-Chip

    DATE'09 Friday Workshop on 3D Integration, Friday 24th April, Nice, France
  • A Novel Methodology for Exploring Interconnection Architectures Targeting 3-D FPGAs

    in 3rd HiPEAC Workshop on Reconfigurable Computing, January 25, 2009, Paphos, Cyprus