Academics

George Lentaris
   Postdoctoral Researcher
   9 Heroon Polytechneiou, Zographou Campus

Dr Lentaris holds a PhD in Computing from the National & Kapodistrian University of Athens (NKUA), Greece, as well as two MSc degrees in “Logic, Algorithms, and Computation” and in “Electronic Automation”, with a BSc in Physics, all awarded by NKUA. His PhD research (conducted during 2006-2011 at the Electronics lab, DST, Physics dpt) resulted in the thesis entitled “Parallel Architectures and Algorithms for Digital Signal and Image Processing”, which contributes in organizing parallel memories for graphics applications and designing motion estimation architectures for video compression.

The research interests of dr Lentaris are, mainly, in parallel algorithms and architectures for applications in signal and image/video processing. His work focuses on digital circuit design and it includes computer vision algorithms, feature extraction, hyperspectral imaging, H.264/AVC encoding, motion estimation techniques, 1D/2D signal interpolation and filtering, OFDM synchronization and baseband processing, FFT implementations, parallel memories organization, as well as process variability and reliability of FPGA devices (incl. radiation testing).

Currently, he is a research associate at Microlab, NTUA, GR, working on high performance embedded computing. More specifically, his work includes HW/SW co-design of computer vision to enhance autonomous rover and/or spacecraft navigation. He is using single-/multi-/SoC-FPGA and DSP platforms to accelerate stereo vision, visual odometry, and pose estimation of uncooperative targets for future missions of ESA. Additionally, he is working on the FPGA implementation of baseband DSP algorithms for novel 5G network technologies.

Personal Webpage: http://users.uoa.gr/~glentaris

    Journals

  • TID evaluation system with on-chip electron source and programmable sensing mechanisms on FPGA

    IEEE Transactions on Nuclear Science, 2019, DOI: 10.1109/TNS.2018.2885713
  • Single- and multi-FPGA acceleration of dense stereo vision for planetary rovers

    ACM Transactions on Embedded Computing Systems, 2019, DOI: 10.1145/3312743
  • In-the-Field Mitigation of Process Variability for Improved FPGA Performance

    IEEE Transactions on Computers, 2019, DOI: 10.1109/TC.2019.2898833
  • High-Performance Vision-Based Navigation on SoC FPGA for Spacecraft Proximity Operations

    IEEE Transactions on Circuits and Systems for Video Technology, 2020, DOI: 10.1109/TCSVT.2019.2900802
  • Analog fiber-wireless downlink transmission of IFoF/mmWave over in-field deployed legacy PON infrastructure for 5G fronthauling

    Journal of Optical Communications and Networking, 2020, DOI: 10.1364/JOCN.391803
  • High-Performance Embedded Computing in Space: Evaluation of Platforms for Vision-Based Navigation

    Journal of Aerospace Information Systems, Feb. 2018 DOI: 10.2514/1.I010555
  • A Flexible, High-Performance FPGA Implementation of a Feed-Forward Equalizer for Optical Interconnects up to 112 Gb/s

    Journal of Signal Processing Systems, 26 November 2016 DOI: 10.1007/s11265-016-1201-y
  • HW/SW co-design and FPGA acceleration of visual odometry algorithms for rover navigation on Mars

    IEEE Transactions on Circuits and Systems for Video Technology, Volume: 26, Issue: 8, Aug. 2016
  • SPARTAN: Developing a Vision System for Future Autonomous Space Exploration Robots

    Journal of Field Robotics, Special Issue: Special Issue on Space Robotics, Part 2, Volume 31, Issue 1, pages 107– 140, January/February 2014

    Workshops

  • A Real-Time, High-Performance FPGA Implementation of a Feed-Forward Equalizer for Optical Interconnects

    in 10th HiPEAC Workshop on Reconfigurable Computing, January 19th, 2016, Prague
  • A Reconfigurable Baseband Architecture for Gbps Wireless 60 GHz Communications

    in DEPCP Friday Workshop,held in conjunction with the DATE 2013 Conference
  • SPARTAN: Efficient Implementation of Computer Vision Algorithms for Autonomous Rover Navigation

    in Workshop on Reconfigurable Computing (WRC), January 21, 2013, Co-located with HiPEAC Conference 2013, Berlin, Germany
  • An FPGA implementation of SURF algorithm for the ExoMars programme

    in Workshop on Reconfigurable Computing (WRC), January 21, 2013, Co-located with HiPEAC Conference 2013, Berlin, Germany
  • Towards Accelarating Computer Vision Algorithms Targeting to Space Applications with a Heterogeneous Platform

    in DATE 2012 Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications (DEPCP 2012), Dresden, Germany, March 12- 16, 2012