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George Lentaris
   Assistant Professor at University of West Attica, Greece

George Lentaris holds a PhD in Computing from the National & Kapodistrian University of Athens (NKUA), Greece, as well as two MSc degrees in “Logic, Algorithms, and Computation” and in “Electronic Automation”, with a BSc in Physics (all awarded by NKUA). His research interests are, generally, in digital circuit design for signal processing. More specifically, his work includes extensive FPGA design, high-performance embedded systems, heterogeneous many-core architectures, parallel architectures and algorithms for applications in: image/video processing, computer vision algorithms, feature extraction, AI convolutional neural networks, hyperspectral image processing, H.264/AVC compression, motion estimation techniques, parallel memories organization, 1D/2D signal interpolation and filtering, FFT implementations, OFDM synchronization and baseband processing in telecommunications, 5G/6G edge computing, AI/ML acceleration, on-board data handling for satallite payloads, as well as process variability and reliability of embedded devices (including radiation testing of FPGA and TPU for space).

Currently, George Lentaris is an assistant professor at the dpt. of Informatics & Computer Engineering at the University of West Attica (UNIWA) and senior researcher at the National Technical University (NTUA), in Athens, Greece. His courses (and/or lab assistance) include Signals and Systems, Digital Circuit Design, Computer Architecture, and Introduction to Parallel Computing. In the past, he was working as a research associate at NTUA for 10+ years (microlab/ECE) and giving multiple lectures at NKUA for Video Compression, Digital Signal Processors, and Embedded Systems. He has participated in more than 18 research projects funded by the European Space Agency, European Commission, and Greece, both as an engineer and technical coordinator. In summary, the projects regarded high-performance embedded computing for space (ESA) and telecom (Horizon). He has co-authored 60+ peer-reviewed papers (21+ in prestigious scientific journals, such as transactions of IEEE and ACM, and 40+ in international conferences), with 730+ total citations, and he has served as a regular reviewer for 14+ journals/conferences (IEEE Trans. on Circuits & Systems for Video Technology, IEEE Trans. on Image Processing, etc.).


  • A Real-Time, High-Performance FPGA Implementation of a Feed-Forward Equalizer for Optical Interconnects

    in 10th HiPEAC Workshop on Reconfigurable Computing, January 19th, 2016, Prague
  • A Reconfigurable Baseband Architecture for Gbps Wireless 60 GHz Communications

    in DEPCP Friday Workshop,held in conjunction with the DATE 2013 Conference
  • SPARTAN: Efficient Implementation of Computer Vision Algorithms for Autonomous Rover Navigation

    in Workshop on Reconfigurable Computing (WRC), January 21, 2013, Co-located with HiPEAC Conference 2013, Berlin, Germany
  • An FPGA implementation of SURF algorithm for the ExoMars programme

    in Workshop on Reconfigurable Computing (WRC), January 21, 2013, Co-located with HiPEAC Conference 2013, Berlin, Germany
  • Towards Accelarating Computer Vision Algorithms Targeting to Space Applications with a Heterogeneous Platform

    in DATE 2012 Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications (DEPCP 2012), Dresden, Germany, March 12- 16, 2012