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Konstantinos Maragos
   FPGA / Digital IC Design Engineer
   9 Heroon Polytechneiou, Zographou Campus


  • A Real-Time, High-Performance FPGA Implementation of a Feed-Forward Equalizer for Optical Interconnects

    in 10th HiPEAC Workshop on Reconfigurable Computing, January 19th, 2016, Prague
  • A Genetic Algorithm Based Partitioning for 3-D Reconfigurable Architectures

    in 9th HiPEAC Workshop on Reconfigurable Computing 2015, WRC 2015, collocated with HiPEAC Conference 2015, Jan. 19-21, 2015, Amsterdam, The Netherlands