Academics

Christoforos Kachris
   Postdoctoral Researcher
   9 Heroon Polytechneiou, Zographou Campus

Christoforos Kachris is a senior research associate at ICCS/NTUA. He is the editor of the book Hardware Accelerators in Data Centers. He has over 15 years of experience on FPGAs (reconfigurable computing), digital design, embedded systems (SoCs), and HW/ SW co-design mainly in network processing, microservers, optical interconnects, and telecommunication systems. He also has more than 10 years experience in EU-funded projects (proposal preparation/writing, researcher, principal investigator, WP leader. He was the technical project manager of VINEYARD h2020 project on the efficient utilization of FPGAs.

Education

– Delft University of Technology Ph.D., Computer Engineering · (2005 – 2008)
– Technical University of Crete / Πολυτεχνείο Κρήτης MSc, Electronic and Computer Engineering · (2001 – 2003)
– Technical University of Crete / Πολυτεχνείο Κρήτης Ptychio, Electronic and Computer Engineer · (1996 – 2001)

    Journals

  • A novel framework for the seamless integration of FPGA accelerators with big data analytics frameworks in heterogeneous data centers

    Proceedings - 2018 International Conference on High Performance Computing and Simulation, HPCS 2018 DOI: 10.1109/HPCS.2018.00090
  • Approximate similarity search with FAISS framework using FPGAs on the cloud

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2019, DOI: 10.1007/978-3-030-27562-4_27
  • BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations

    Journal of Neural Engineering, Vol. 14, No. 6, 2017 DOI: 10.1088/1741-2552/aa7fc5
  • An FPGA-based Integrated MapReduce Accelerator Platform

    Journal of Signal Processing Systems 2017
  • A Survey on FEC Codes for 100G and Beyond Optical Networks

    IEEE Communications: Surveys and Tutorials, 27 January 2016
  • A MapReduce Scratchpad Memory for Multi–core Cloud Computing Applications

    Microprocessors and Microsystems (MICPRO), 39 (2015)

    Conferences

  • VineTalk: Simplifying software access and sharing of FPGAs in datacenters

    2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017 DOI: 10.23919/FPL.2017.8056788
  • FPGA acceleration of spark applications in a Pynq cluster

    2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017 DOI: 10.23919/FPL.2017.8056815
  • SPynq: Acceleration of machine learning applications over Spark on Pynq

    Proceedings - 2017 17th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2017 DOI: 10.1109/SAMOS.2017.8344613
  • Hardware accelerators for financial applications in HDL and High Level Synthesis

    Proceedings - 2017 17th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2017 DOI: 10.1109/SAMOS.2017.8344641
  • Acceleration of image classification with Caffe framework using FPGA

    2018 7th International Conference on Modern Circuits and Systems Technologies, MOCAST 2018 DOI: 10.1109/MOCAST.2018.8376580
  • The VINEYARD integrated framework for hardware accelerators in the cloud

    ACM International Conference Proceeding Series DOI: 10.1145/3229631.3236093
  • Hardware Acceleration on Gaussian Naive Bayes Machine Learning Algorithm

    2019 8th International Conference on Modern Circuits and Systems Technologies, MOCAST 2019, DOI: 10.1109/MOCAST.2019.8741875
  • Modular FPGA Acceleration of Data Analytics in Heterogenous Computing

    Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019, DOI: 10.23919/DATE.2019.8715018
  • Automatic Generation of FPGA Kernels from Open Format CNN Models

    Proceedings - 28th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2020, DOI: 10.1109/FCCM48280.2020.00070
  • Hardware Acceleration of Decision Tree Learning Algorithm

    2020 9th International Conference on Modern Circuits and Systems Technologies, MOCAST 2020, DOI: 10.1109/MOCAST49295.2020.9200255
  • High-Performance Hardware Accelerators for Solving Ordinary Differential Equations

    in 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), 2017
  • Spark acceleration on FPGAs: A use case on the machine learning in Pynq

    in Proc. of The International Conference on Modern Circuits and Systems Technologies (MOCAST), 2017
  • A Survey on Reconfigurable Accelerators for Cloud Computing

    in Proc. of International Conference on Field-Programmable Logic and Applications (FPL), 2016
  • Performance and Energy evaluation of Spark applications on low-power SoCs

    in Proc. of International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2016
    • Christoforos Kachris ,
    • Dimitrios Soudris ,
    • Georgi Gaydajiev ,
    • Huy-Nam Nguyen ,
    • Dimitrios Nikopoulos ,
    • Angelos Bilas ,
    • Neil Morgan ,
    • Christos Strydis ,
    • Vasilis Spatadakis ,
    • Dimitris Gardelis ,
    • Ricardo Jimenez-Peris and
    • Alexandre Almeida

    The VINEYARD project: Versatile Integrated Accelerator-based Heterogeneous Data Centers

    in Proc. of 5th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2016
    • Christoforos Kachris ,
    • Dimitrios Soudris ,
    • Georgi Gaydajiev ,
    • Huy-Nam Nguyen ,
    • Dimitrios Nikopoulos ,
    • Angelos Bilas ,
    • Neil Morgan ,
    • Christos Strydis ,
    • Christos Tsalidis ,
    • John Balafas ,
    • Ricardo Jimenez-Peris and
    • Alexandre Almeida

    The VINEYARD approach: Versatile, Integrated, Accelerator based, Heterogeneous Data Centers

    in Applied Reconfigurable Computing (ARC), 2016
  • A Reconfigurable MapReduce Accelerator for multi-core all-programmable SoCs

    in Proceedings of International Symposium on Systemon-Chip (SOC), 2014
  • Reconfigurable FEC Codes for Software-defined Optical Transceivers

    in Proceedings of 13th International Conference on Optical Communications and Networks (ICOCN), 2014
  • A Low-Latency Algorithm and FPGA Design for the Min-Search of LDPC Decoders

    in Proceedings of 21st Reconfigurable Architectures Workshop (RAW), 2014
  • A Configurable MapReduce Accelerator for Multi-core FPGAs

    in Proceedings of 22nd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2014
  • Automatic Implementation of Low-Complexity QC-LDPC Encoders

    in Proceedings of 23th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2013
  • A Low-Complexity Implementation of QC-LDPC Encoder In Reconfigurable Logic

    in 23rd International Conference on Field Programmable Logic and Applications (FPL), 2013
  • Performance Evaluation of Embedded Processor in MapReduce Cloud Computing Applications

    in Proccedings of 3rd International Conference on Cloud Computing (CLOUDCOMP), 2012

    Workshops

  • High Level Synthesis versus HDL: A Case study on Hardware Accelerators for Financial Appliacations

    in WRC: 11th HiPEAC Workshop on Reconfigurable Computing, Monday, Jan. 23, 10:00 - 17:30, Stockholm 2017

    Article

  • Seamless FPGA deployment over spark in cloud computing: A use case on machine learning hardware acceleration

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) DOI: 10.1007/978-3-319-78890-6_54
  • Efficient hardware acceleration of recommendation engines: A use case on collaborative filtering

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) DOI: 10.1007/978-3-319-78890-6_6