Kiamal Pekmestzi

Emeritus Professor

2107723548

pekmes@microlab.ntua.gr

9 Heroon Polytechneiou, Zographou Campus

Books

N. Weste ,
D.M. Harris Eshraghian ,
Dimitrios Soudris ,
Kiamal Pekmestzi and
Costas Goutis

Σχεδίαση ολοκληρωμένων κυκλωμάτων CMOS VLSI(3rd edition)

Εκδόσεις Παπασωτηρίου 2010

N. Weste ,
D.M. Harris Eshraghian ,
Dimitrios Soudris ,
Kiamal Pekmestzi and
Costas Goutis

Σχεδίαση ολοκληρωμένων κυκλωμάτων CMOS VLSI

Εκδόσεις Παπασωτηρίου 1996

Book Chapters

“A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning,” Book Chapter in “Designing Very Large Scale Integration Systems: Emerging Trends & Challenges”

Editors: N. Voros, A. Mukherjee, N. Sklavos, K. Masselos, M. Huebner, Springer 2011

Journals

Walking through the Energy-Error Pareto Frontier of Approximate Multipliers

IEEE Micro DOI: 10.1109/MM.2018.043191124

Multi-Level Approximate Accelerator Synthesis under Voltage Island Constraints

IEEE Transactions on Circuits and Systems II: Express Briefs, 2019, DOI: 10.1109/TCSII.2018.2869025

Energy-efficient VLSI implementation of multipliers with double LSB operands

IET Circuits, Devices and Systems, 2019, DOI: 10.1049/iet-cds.2018.5039

VOSsim: A Framework for Enabling Fast Voltage Over-Scaling Simulation for Approximate Computing Circuits

IEEE Transactions on Very Large Scale Integration Systems, Volume: 26, Issue: 6, June 2018 DOI: 10.1109/TVLSI.2018.2803202

Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers

IEEE Transactions On Very Large Scale Integration (VLSI) Systems, 26 (3), 2018 DOI: 10.1109/TVLSI.2017.2767858

DIRT latch: A novel low cost double node upset tolerant latch

Microelectronics Reliability, Vol. 68, Pages 57-68, Jan. 2017

DesignEfficient Approximate Multiplication Circuits Through Partial Product Perforation

IEEE Transactions on Very Large Scale Integration Systems (VLSI), 2016

Dimitrios Stamoulis ,
Kostas Tsoumanis ,
Dimitris Rodopoulos ,
Brett H. Meyer ,
Kiamal Pekmestzi ,
Dimitrios Soudris and
Zeljko Zilic

Efficient variability analysis of arithmetic units using linear regression techniques

Analog Integrated Circuits and Signal Processing, Springer, (2016)

Low latency radiation tolerant self-repair reconfigurable SRAM architecture

Microelectronics Reliability, Vol. 56, Pages 202-211, Jan. 2016

Compiler-in-the-Loop Exploration During Datapath Synthesis for Higher Quality Delay-Area Trade-offs

ACM TODAES, Transactions on Design Automation of Electronic Systems, Vol. 18, No. 1, Article 11, December 2012

Sotirios Xydis ,
Christoforos Economakos ,
Dimitrios Soudris and
Kiamal Pekmestzi

High Performance and Area Efficient Flexible DSP Datapath Synthesis

IEEE Transactions on VLSI Systems, 19, No. 3, March 2011

Conferences

Efficient support vector machines implementation on Intel/Movidius Myriad 2

2018 7th International Conference on Modern Circuits and Systems Technologies, MOCAST 2018 DOI: 10.1109/MOCAST.2018.8376630

TF2FPGA: A Framework for Projecting and Accelerating Tensorflow CNNs on FPGA Platforms

2019 8th International Conference on Modern Circuits and Systems Technologies, MOCAST 2019, DOI: 10.1109/MOCAST.2019.8741940

Cooperative arithmetic-aware approximation techniques for energy-efficient multipliers

Proceedings - Design Automation Conference, 2019, DOI: 10.1145/3316781.3317793

Combining arithmetic approximation techniques for improved CNN circuit design

ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings, DOI: 10.1109/ICECS49266.2020.9294869

Multi-Level Approximation for Inexact Accelerator Synthesis Under Voltage Island Constraints

in Workshop on Approximate Computing, 2016

Low leakage radiation tolerant CAM/TCAM cell

IEEE 21st International On-Line Testing Symposium (IOLTS), Pages 206-211, 6-8 Jul. 2015

Nikolaos Eftaxiopoulos Sarris ,
N. Axelos ,
Georgios Zervakis ,
Kostas Tsoumanis and
Kiamal Pekmestzi

Delta DICE: A Double Node Upset resilient latch

IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), Pages 1-4, 2-5 Aug. 2015

Georgios Zervakis ,
Nikolaos Eftaxiopoulos Sarris ,
Kostas Tsoumanis ,
N. Axelos and
Kiamal Pekmestzi

A segmentation-based BISR scheme

19th Asia and South Pacific Design Automation Conference (ASP-DAC), Pages 652-657, 20-23 Jan. 2014

N. Axelos ,
Nikolaos Eftaxiopoulos Sarris ,
Georgios Zervakis ,
Kostas Tsoumanis and
Kiamal Pekmestzi

FF-DICE: An 8T soft-error tolerant cell using Independent Dual Gate SOI FinFETs

IEEE 20th International On-Line Testing Symposium (IOLTS), Pages 200-201, 7-9 Jul. 2014

Nikolaos Eftaxiopoulos Sarris ,
N. Axelos ,
Georgios Zervakis ,
Kostas Tsoumanis and
Kiamal Pekmestzi

An independent dual gate SOI FinFET soft-error resilient memory cell

9th International Design & Test Symposium (IDT), Pages 39-44, 16-18 Dec. 2014

Georgios Zervakis ,
Nikolaos Eftaxiopoulos Sarris ,
Kostas Tsoumanis ,
N. Axelos and
Kiamal Pekmestzi

A high radix montgomery multiplier with concurrent error detection

9th International Design & Test Symposium (IDT), Pages 199-204, 16-18 Dec. 2014

High performance MAC designs

9th International Design & Test Symposium (IDT), Pages 30-35, 16-18 Dec. 2014

A radiation tolerant and self-repair memory cell

IEEE 19th International On-Line Testing Symposium (IOLTS), Pages 210-215, 8-10 Jul. 2013

Dimitris Bekiaris ,
Antonis Papanikolaou ,
G. Stamelos ,
Dimitrios Soudris ,
George Economakos and
Kiamal Pekmestzi

A standard cell library suite for deep-deep sub-micron CMOS technologies

in Proceedings of 6th International conference on Design & Technology of Integrated Systems in nanoscale era (DTIS), 2011

Dimitris Bekiaris ,
Antonis Papanikolaou ,
Ch. Papameletis ,
Dimitrios Soudris ,
George Economakos and
Kiamal Pekmestzi

A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework

in Proc. of PATMOS 2010, International Workshop on Power And Timing Modeling, Optimization and Simulation, 2010

Custom Multi-Threaded Dynamic Memory Management for Multiprocessor System-on-Chip Platforms

in Proceedings - 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2010

High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures

in Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2010

Sotirios Xydis ,
Christos Skouroumounis ,
Kiamal Pekmestzi ,
Dimitrios Soudris and
George Economakos

Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching

in Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2010

Sotirios Xydis ,
Christos Skouroumounis ,
Kiamal Pekmestzi ,
Dimitrios Soudris and
George Economakos

Designing Efficient DSP Datapaths Through Compiler-in-the-Loop Exploration Methodology

in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), 2010

Joint Exploitation of Horizontal/Vertical Parallelism and Operation Chaining for Flexible DSP Synthesis

in IFIP/IEEE International Conference on VLSI -SOC, 2008

Mapping DSP Applications onto HighPerformance Architectural Templates with Inlined Flexibility

in Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2008

Workshops

D. Mpekiaris ,
Antonis Papanikolaou ,
Dimitrios Soudris ,
George Economakos and
Kiamal Pekmestzi

Reliability Breakdown Analysis of an MP-SoC platform due to Interconnect Wear-out

in 2nd HiPEAC Workshop on Design for Reliability (DFR’10) January 24th, 2010 Pisa, ITALY

Implementation of Approximate Convolutional Filters and Floating-Point Components for CNN Applications

Academic Advisors: Kiamal Pekmestzi and Vasileios Leon

Brief: PDF

Implementation of Approximate Convolutional Filters and Floating-Point Components for CNN Applications

Academic Advisors: Kiamal Pekmestzi and Vasileios Leon

Brief: PDF

Academics

Books

Σχεδίαση ολοκληρωμένων κυκλωμάτων CMOS VLSI(3rd edition)

Σχεδίαση ολοκληρωμένων κυκλωμάτων CMOS VLSI

Book Chapters

“A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning,” Book Chapter in “Designing Very Large Scale Integration Systems: Emerging Trends & Challenges”

Journals

Walking through the Energy-Error Pareto Frontier of Approximate Multipliers

Multi-Level Approximate Accelerator Synthesis under Voltage Island Constraints

Energy-efficient VLSI implementation of multipliers with double LSB operands

VOSsim: A Framework for Enabling Fast Voltage Over-Scaling Simulation for Approximate Computing Circuits

Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers

DIRT latch: A novel low cost double node upset tolerant latch

DesignEfficient Approximate Multiplication Circuits Through Partial Product Perforation

Efficient variability analysis of arithmetic units using linear regression techniques

Low latency radiation tolerant self-repair reconfigurable SRAM architecture

Compiler-in-the-Loop Exploration During Datapath Synthesis for Higher Quality Delay-Area Trade-offs

High Performance and Area Efficient Flexible DSP Datapath Synthesis

Conferences

Efficient support vector machines implementation on Intel/Movidius Myriad 2

TF2FPGA: A Framework for Projecting and Accelerating Tensorflow CNNs on FPGA Platforms

Cooperative arithmetic-aware approximation techniques for energy-efficient multipliers

Combining arithmetic approximation techniques for improved CNN circuit design

Multi-Level Approximation for Inexact Accelerator Synthesis Under Voltage Island Constraints

Low leakage radiation tolerant CAM/TCAM cell

Delta DICE: A Double Node Upset resilient latch

A segmentation-based BISR scheme

FF-DICE: An 8T soft-error tolerant cell using Independent Dual Gate SOI FinFETs

An independent dual gate SOI FinFET soft-error resilient memory cell

A high radix montgomery multiplier with concurrent error detection

High performance MAC designs

A radiation tolerant and self-repair memory cell

A standard cell library suite for deep-deep sub-micron CMOS technologies

A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework

Custom Multi-Threaded Dynamic Memory Management for Multiprocessor System-on-Chip Platforms

High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures

Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching

Designing Efficient DSP Datapaths Through Compiler-in-the-Loop Exploration Methodology

Joint Exploitation of Horizontal/Vertical Parallelism and Operation Chaining for Flexible DSP Synthesis

Mapping DSP Applications onto HighPerformance Architectural Templates with Inlined Flexibility

Workshops

Reliability Breakdown Analysis of an MP-SoC platform due to Interconnect Wear-out

Implementation of Approximate Convolutional Filters and Floating-Point Components for CNN Applications

Implementation of Approximate Convolutional Filters and Floating-Point Components for CNN Applications