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DTSTART:20190101T000000
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BEGIN:VEVENT
DTSTART;TZID=Europe/Moscow:20210401T103000
DTEND;TZID=Europe/Moscow:20210402T120000
DTSTAMP:20210401T085418Z
CREATED:20210401T085135Z
LAST-MODIFIED:20210401T085418Z
UID:5660-1617273000-1617364800@microlab.ntua.gr
SUMMARY:Tech Talk #18 – Neural Network Accelerators: From Physics to System with a Cool Approximation
DESCRIPTION:Την Παρασκευή 4/2/2021 και ώρα 10:30 EEST (Greek Time) θα έχουμε την παρουσίαση για τα Fridays Tech Talks από τoν μεταδιδάκτορα Γεώργιο Ζερβάκη με τίτλο: \n\n“Neural Network Accelerators: From Physics to System with a Cool Approximation” \n\nΗ παρουσίαση θα γίνει μέσω webex στο παρακάτω link Webex. \nΑκολουθεί μία σύντομη περίληψη της παρουσίασης: \n“Modern systems\, from the ultra-low power to the HPC domain\, rely more and more on deep neural networks (DNNs) to deliver sophisticated services. To satisfy tighter and tighter latency requirements\, ASIC inference accelerators are becoming mainstream. Inference accelerators perform thousands of MAC operations per cycle\, packing immense computational power in a very confined area\, leading thus to elevated power densities and unsustainable on-chip temperature. To further boost the performance of DNN accelerators while satisfying strict temperature and energy constraints\, radical departures to conventional approaches are mandatory. In this talk\, we present a holistic evaluation\, from the device level all the way up to the system level where inference accuracy is affected\, of DNN accelerators. We evaluate the impact that emerging technology (NCFET)\, emerging cooling (Superlattice Thermoelectric Cooling)\, and emerging computing (Approximate Computing) have on future DNN accelerators in terms of accuracy\, efficiency\, temperature\, and/or performance.”
URL:https://microlab.ntua.gr/event/tech-talk-18-neural-network-accelerators-from-physics-to-system-with-a-cool-approximation/
CATEGORIES:Tech Talks
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Moscow:20210325T100000
DTEND;TZID=Europe/Moscow:20210326T233000
DTSTAMP:20210325T121030Z
CREATED:20210325T121030Z
LAST-MODIFIED:20210325T121030Z
UID:5636-1616666400-1616801400@microlab.ntua.gr
SUMMARY:Tech Talk #17 – Cloud computing: Past\, Present and Future Challenges
DESCRIPTION:Την Παρασκευή 26/3/2021 και ώρα 10:00 EET (Greek Time) θα έχουμε την παρουσίαση για τα Fridays Tech Talks από τoν υποψήφιo διδάκτορα Δημοσθένη Μασούρο με τίτλο: \n\n“Cloud Computing: Past\, Present and Future Challenges” \n\nΗ παρουσίαση θα γίνει μέσω webex στο παρακάτω link Webex. \nΑκολουθεί μία σύντομη περίληψη της παρουσίασης: \n“Today\, cloud computing has transitioned to become a mainstream technology\, with many different types of cloud computing to choose from. Cloud computing is the delivery of computing services—including servers\, storage\, databases\, networking\, software\, analytics\, and intelligence—over the Internet to offer faster innovation\, flexible resources\, and economies of scale. Even though cloud computing offers a huge variety of benefits to end-users\, these benefits do not come “for free”. From its inception up to today\, many challenges had to be resolved and there are many more to come. Are we ready to handle them?”
URL:https://microlab.ntua.gr/event/tech-talk-17-cloud-computing-past-present-and-future-challenges/
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Moscow:20210319T100000
DTEND;TZID=Europe/Moscow:20210319T233000
DTSTAMP:20210318T090306Z
CREATED:20210318T090144Z
LAST-MODIFIED:20210318T090306Z
UID:5626-1616148000-1616196600@microlab.ntua.gr
SUMMARY:Tech Talk #16 – Energy Efficient (green) computing: what does that really mean?
DESCRIPTION:Την Παρασκευή 19/3/2021 και ώρα 10:00 EET (Greek Time) θα έχουμε την παρουσίαση για τα Fridays Tech Talks από τoν υποψήφιo διδάκτορα Χάρη Μάραντο με τίτλο: \n\n“Energy Efficient (green) computing: what does that really mean?” \n\nΗ παρουσίαση θα γίνει μέσω webex στο παρακάτω link Webex. \nΑκολουθεί μία σύντομη περίληψη της παρουσίασης: \n“Green\, sustainable or energy efficient computing terms are gaining more and more attention lately. However\, the relevant works found in the literature are very different. On the one hand\, from the software engineering perspective\, there are tools that suggest best practices and guidelines for software development based on empirical studies\, without detailed analysis\, specific structure and tool support. On the other hand\, from the embedded systems / hardware engineering point of view we can find these terms in approaches that use custom microarchitecture techniques\, DSPs\, alternative utilization of the memory hierarchy etc. There are also articles claiming that software engineers either do not take energy into account or lack knowledge in this area. So let’s discuss: What do we have now\, what is missing\, what can we do?”
URL:https://microlab.ntua.gr/event/tech-talk-16-energy-efficient-green-computing-what-does-that-really-mean/
CATEGORIES:Tech Talks
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Moscow:20210312T100000
DTEND;TZID=Europe/Moscow:20210312T113000
DTSTAMP:20210310T174534Z
CREATED:20210310T174534Z
LAST-MODIFIED:20210310T174534Z
UID:5619-1615543200-1615548600@microlab.ntua.gr
SUMMARY:Tech Talk #15 – Approximate CNN Topologies: A survey
DESCRIPTION:Την Παρασκευή 12/3/2021 και ώρα 10:00 EET (Greek Time) θα έχουμε την παρουσίαση για τα Fridays Tech Talks από τoν υποψήφιo διδάκτορα Γιώργο Αρμενιάκο με τίτλο: \n\n“Approximate CNN Topologies: A survey” \n\nΗ παρουσίαση θα γίνει μέσω webex στο παρακάτω link Webex. \nΑκολουθεί μία σύντομη περίληψη της παρουσίασης: \n“Convolutional Neural Networks (CNNs) are becoming popular because of their high performance and accuracy in various cognitive tasks in Machine Learning (ML). However\, applications using deep neural networks are highly computationally intensive and\, therefore\, the need to reduce their energy consumption and demands in memory is rising. Approximate Computing (AC) has emerged as a means for improving the performance and efficiency of computing systems. The fact that deep CNNs are inherently error resilient makes Approximate Computing a solution to their high computation and storage demands. This presentation aims to provide a comprehensive survey and a comparative evaluation of recently developed approximate techniques used in (deep) CNNs. We will first introduce some key properties of convolutional neural networks which are exploited by different approximate methods. Then\, we will analyze these approximation techniques and discuss their advantages and limitations.”
URL:https://microlab.ntua.gr/event/tech-talk-15-approximate-cnn-topologies-a-survey/
CATEGORIES:Tech Talks
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Moscow:20210305T100000
DTEND;TZID=Europe/Moscow:20210305T113000
DTSTAMP:20210304T141020Z
CREATED:20210304T140305Z
LAST-MODIFIED:20210304T141020Z
UID:5609-1614938400-1614943800@microlab.ntua.gr
SUMMARY:Tech Talk #14 – 5G: A new era in telecommunications
DESCRIPTION:Την Παρασκευή 5/3/2021 και ώρα 10:00 EET (Greek Time) θα έχουμε την παρουσίαση για τα Fridays Tech Talks από τoν υποψήφιo διδάκτορα Ιωάννη Στρατάκο με τίτλο: \n\n“5G: A new era in telecommunications” \n\nΗ παρουσίαση θα γίνει μέσω webex στο παρακάτω link Webex. \nΑκολουθεί μία σύντομη περίληψη της παρουσίασης: \n“5G is considered by many as the technology platform that has the potential to revolutionize the established telecommunication landscape and the way people interact with their social and economic surroundings in their everyday life\, supporting the fully automated factories of the future\, smart cities\, autonomous vehicles\, mixed reality applications\, and cloud/edge computing. This presentation will focus 1) on key technologies that will be utilized in 5G network infrastructures\, 2) the approach to realize such networks within the 5G-PHOS project and 3) how state-of-the-art FPGA devices can be used for rapid-prototyping of a Baseband Processing Unit (BBU).”
URL:https://microlab.ntua.gr/event/tech-talk-14-5g-a-new-era-in-telecommunications/
CATEGORIES:Tech Talks
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Moscow:20210226T100000
DTEND;TZID=Europe/Moscow:20210226T113000
DTSTAMP:20210225T082241Z
CREATED:20210225T082241Z
LAST-MODIFIED:20210225T082241Z
UID:5571-1614333600-1614339000@microlab.ntua.gr
SUMMARY:Tech Talk #13 – A dataflow accelerator for short read alignment on NGS data
DESCRIPTION:Την Παρασκευή 26/2/2021 και ώρα 10:00 EET (Greek Time) θα έχουμε την παρουσίαση για τα Fridays Tech Talks από την υποψήφια διδάκτορα Κωσταντίνα Κολιογεώργη με τίτλο: \n\n“A dataflow accelerator for short read alignment on NGS data” \n\nΗ παρουσίαση θα γίνει μέσω webex στο παρακάτω link Webex. \nΑκολουθεί μία σύντομη περίληψη της παρουσίασης: \n“Next Generation Sequencing (NGS) technologies have revolutionised genome study through rapid generation of genomics data at low cost. Any genome analysis usually starts with DNA read alignment\, employing string-matching algorithms such as Smith-Waterman to compare DNA sequences. The inherent computational intensity and the vast amount of NGS input data the algorithm operates on\, create a bottleneck in the workflow. Accelerated reconfigurable computing has been extensively leveraged to alleviate this bottleneck\, focusing mostly on high-performance albeit standalone implementations\, i.e neglecting the implications of integrating the accelerated functions within the sequencing tools. In existing accelerated solutions effective co-design of the NGS short-read alignment still remains an open issue\, mainly due to narrow view on real integration aspects\, such as system wide communication and accelerator call overheads. In this paper\, we address the aforementioned inefficiencies in a twofold manner. We first propose a novel dataflow architecture for Smith-Waterman Matrix-fill and Traceback stages to perform high throughput short-read alignment on NGS data. We then couple the FPGA accelerator with radical software restructurings to widely-used Bowtie2 aligner. Moving both Matrix-fill and Traceback on chip extinguishes the communication data overheads whereas software restructuring accommodates batch alignment and minimizes calling overhead. The proposed solution delivers up to x116 and x2 speedup over state of the art software and hardware accelerators respectively\, as well as up to x1.9 speedup for an end-to-end accelerated third-party aligner.”
URL:https://microlab.ntua.gr/event/tech-talk-13-a-dataflow-accelerator-for-short-read-alignment-on-ngs-data/
CATEGORIES:Tech Talks
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Moscow:20210217T100000
DTEND;TZID=Europe/Moscow:20210217T233000
DTSTAMP:20210217T141829Z
CREATED:20210217T135414Z
LAST-MODIFIED:20210217T141829Z
UID:5399-1613556000-1613604600@microlab.ntua.gr
SUMMARY:Tech Talk #12 – AI Chip Landscape and Observations
DESCRIPTION:Την Παρασκευή 19/2/2021 και ώρα 10:00 EET (Greek Time) θα έχουμε την παρουσίαση για τα Fridays Tech Talks από τον υποψήφιο διδάκτορα Δημήτρη Δανόπουλο με τίτλο: \n\n“AI Chip Landscape and Observations” \n\nΗ παρουσίαση θα γίνει μέσω webex στο παρακάτω link Webex. \nΑκολουθεί μία σύντομη περίληψη της παρουσίασης: \n“Many powerful AI/ML applications exist and are being developed\, but many also require enormous computational power — often at scales only available to the largest companies. Improving performance and speed while keeping compute cost and power demands low is the central challenge both in edge and cloud computations. Especially now that we’ve reached the scale of nanometers\, meaning we’re up against the limitations of physics. If major breakthroughs in silicon architecture efficiency don’t happen\, AI will suffer an unevenly distributed future and the population miss out on the improvements AI could make to their lives. This presentation will describe the next generation of AI chips and several companies\, especially startups which design and build their custom AI hardware for edge and cloud AI workloads. “
URL:https://microlab.ntua.gr/event/tech-talk-12-ai-chip-landscape-and-observations/
CATEGORIES:Tech Talks
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Moscow:20210205T100000
DTEND;TZID=Europe/Moscow:20210205T233000
DTSTAMP:20210204T094118Z
CREATED:20210204T092130Z
LAST-MODIFIED:20210204T094118Z
UID:5095-1612519200-1612567800@microlab.ntua.gr
SUMMARY:Tech Talk #11 – LOOG: A Case For Non-Conventional GPU Architectures
DESCRIPTION:Την Παρασκευή 5/2/2021 και ώρα 10:00 EET (Greek Time) θα έχουμε την παρουσίαση για τα Fridays Tech Talks από τον υποψήφιο διδάκτορα Κωστή Ηλιάκη με τίτλο: \n\n“LOOG: A Case For Non-Conventional GPU Architectures” \n\nΗ παρουσίαση θα γίνει μέσω webex στο παρακάτω link Webex. \nΑκολουθεί μία σύντομη περίληψη της παρουσίασης: \n“GPU is the dominant platform for accelerating general-purpose workloads due to its computing capacity and cost-efficiency. GPU applications cover an ever-growing range of domains. To achieve high throughput\, GPUs rely on massive multi-threading and fast context switching to overlap computations with memory operations. We observe that among the diverse GPU workloads\, there exists a significant class of kernels that fail to maintain a sufficient number of active warps to hide the latency of memory operations\, and thus suffer from frequent stalling. We argue that the dominant Thread-Level Parallelism model is not enough to efficiently accommodate the variability of modern GPU applications. To address this inherent inefficiency\, we propose LOOG\, a novel micro-architecture with lightweight Out-Of-Order execution capability enabling Instruction-Level Parallelism to complement the conventional Thread-Level Parallelism model. To minimize the hardware overhead\, we carefully design our extension to highly re-use the existing micro-architectural structures and study various design trade-offs to contain the overall area and power overhead\, while providing improved performance. We show that the proposed architecture outperforms conventional platforms by 23% on average for low-occupancy kernels\, with an area and power overhead of 1.29% and 10.05%\, respectively. Finally\, we establish the potential of our proposal as a micro-architecture alternative by providing 16% speedup over a wide collection of 60 general-purpose kernels.”
URL:https://microlab.ntua.gr/event/tech-talk-11-loog-a-case-for-non-conventional-gpu-architectures/
CATEGORIES:Tech Talks
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Moscow:20210129T100000
DTEND;TZID=Europe/Moscow:20210129T233000
DTSTAMP:20210126T102802Z
CREATED:20210126T102708Z
LAST-MODIFIED:20210126T102802Z
UID:5090-1611914400-1611963000@microlab.ntua.gr
SUMMARY:Tech Talk #10 – Improving Performance-Power-Programmability in Space Avionics with COTS Devices: Pose Tracking on Myriad2
DESCRIPTION:Την Παρασκευή 29/1/2021 και ώρα 10:00 EET (Greek Time) θα έχουμε την παρουσίαση για τα Fridays Tech Talks από τον υποψήφιο διδάκτορα Βασίλη Λέων με τίτλο: \n\n“Improving Performance-Power-Programmability in Space Avionics with COTS Devices: Pose Tracking on Myriad2″ \n\nΗ παρουσίαση θα γίνει μέσω webex στο παρακάτω link Webex. \nΑκολουθεί μία σύντομη περίληψη της παρουσίασης: \n“The advent of powerful edge devices and AI algorithms has already revolutionized many terrestrial applications\, however\, for both technical and historical reasons\, the space industry is still striving to adopt these key enabling technologies in new mission concepts. In this context\, we evaluate an heterogeneous multi-core SoC processor for use on-board future spacecraft to support novel\, computationally-demanding DSP and AI functionalities. Given the importance of low power consumption in satellites\, we consider the Intel Movidius Myriad2 SoC and focus on SW development and performance aspects. We design a methodology and framework to accommodate efficient partitioning\, mapping\, parallelization\, code optimization\, and tuning of complex algorithms. Furthermore\, we propose an avionics architecture combining this Commercial-Off-The-Self (COTS) chip with an FPGA device to facilitate\, among others\, interfacing with traditional space instruments via SpaceWire transcoding. We prototype our architecture in the lab targeting Vision-Based Navigation (VBN) tasks. We implement a representative computer vision pipeline to track the 6D pose of ENVISAT using Megapixel images during hypothetical spacecraft proximity operations. Overall\, we achieve 2.6-4.9 FPS with only 0.8-1.1W on Myriad2\, i.e.\, tenfold acceleration versus modern rad-hard processors. Based on the results\, we assess various benefits of utilizing Myriad2 instead of conventional FPGAs and CPUs. “
URL:https://microlab.ntua.gr/event/tech-talk-10-improving-performance-power-programmability-in-space-avionics-with-cots-devices-pose-tracking-on-myriad2/
CATEGORIES:Tech Talks
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Moscow:20201215T100000
DTEND;TZID=Europe/Moscow:20201215T113000
DTSTAMP:20201215T173455Z
CREATED:20201215T173455Z
LAST-MODIFIED:20201215T173455Z
UID:5064-1608026400-1608031800@microlab.ntua.gr
SUMMARY:Tech Talk #9 - GPU sharing for ML workloads on cloud infrastructures
DESCRIPTION:Την Παρασκευή 18/12/2020 και ώρα 10:00 EET (Greek Time) θα έχουμε την παρουσίαση για τα Fridays Tech Talks από τον υποψήφιο διδάκτορα Άγγελο Φερίκογλου με τίτλο: \n\n“GPU sharing for ML workloads on cloud infrastructures” \n\nΗ παρουσίαση θα γίνει μέσω webex στο παρακάτω link Webex. \nΑκολουθεί μία σύντομη περίληψη της παρουσίασης: \n“Nowadays\, there is an ever-increasing number of machine learning workloads pushed and executed on the cloud. To effectively serve and manage the computational demands\, data center operators have provisioned their infrastructures with accelerators. Specifically for GPUs\, support for efficient management lacks\, as state of the art schedulers and orchestrators\, treat GPUs only as a typical compute resources ignoring their unique characteristics and application properties. Both academia and industry introduced mechanisms that aim to overcome the abovementioned limitation. In this presentation\, representative existing works and future challenges will be presented. “
URL:https://microlab.ntua.gr/event/tech-talk-9-gpu-sharing-for-ml-workloads-on-cloud-infrastructures/
CATEGORIES:Tech Talks
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Moscow:20201211T100000
DTEND;TZID=Europe/Moscow:20201211T113000
DTSTAMP:20201208T154247Z
CREATED:20201208T151106Z
LAST-MODIFIED:20201208T154247Z
UID:5055-1607680800-1607686200@microlab.ntua.gr
SUMMARY:Tech Talk #8 - Automatic Optimization Heuristics for Workloads Mapping on GPUs
DESCRIPTION:Την Παρασκευή 11/12/2020 και ώρα 10:00 EET (Greek Time) θα έχουμε την παρουσίαση για τα Fridays Tech Talks από τον υποψήφιο διδάκτορα Ιωάννη Ορούτζογλου με τίτλο: \n\n“Automatic Optimization Heuristics for Workloads Mapping on GPUs” \n\nΗ παρουσίαση θα γίνει μέσω webex στο παρακάτω link Webex. \nΑκολουθεί μία σύντομη περίληψη της παρουσίασης: \n“Despite the fact that the programmability of GPUs as general purpose accelerators has been improved significantly over the past years\, achieving close-to-peak performance remains a demanding task. While expert programmers might face multiple GPU program’s optimization problems where the space of design decisions is too large to explore\, there is a need to automatically tune their workloads in terms of performance for a single or various architectures. Therefore\, accurate automatic optimization heuristics are necessary for dealing with the complexity and diversity of modern hardware and software of GPUs in order to lead to optimal design decisions with less human effort. Representative existing works and future challenges will be presented.”
URL:https://microlab.ntua.gr/event/tech-talk-8-automatic-optimization-heuristics-for-workloads-mapping-on-gpus/
CATEGORIES:Tech Talks
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Moscow:20201202T100000
DTEND;TZID=Europe/Moscow:20201202T233000
DTSTAMP:20201202T120734Z
CREATED:20201202T120145Z
LAST-MODIFIED:20201202T120734Z
UID:5029-1606903200-1606951800@microlab.ntua.gr
SUMMARY:Tech Talk #7 - The Coronavirus Pandemic as a Boost for IOT Applications that came to stay : The Industry Changes
DESCRIPTION:Την Παρασκευή 04/12/2020 και ώρα 10:00 EET (Greek Time) θα έχουμε την παρουσίαση για τα Fridays Tech Talks από τον υποψήφιο διδάκτορα Γρηγόρη Προίσκο με τίτλο: \n\n“The Corona virus Pandemic as a Boost for IOT Applications that came to stay : The Industry Changes” \n\nΗ παρουσίαση θα γίνει μέσω webex στο παρακάτω link Webex.
URL:https://microlab.ntua.gr/event/tech-talk-7-the-corona-virus-pandemic-as-a-boost-for-iot-applications-that-came-to-stay/
CATEGORIES:Tech Talks
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Moscow:20201127T150000
DTEND;TZID=Europe/Moscow:20201127T163000
DTSTAMP:20201125T165959Z
CREATED:20201125T165137Z
LAST-MODIFIED:20201125T165959Z
UID:5025-1606489200-1606494600@microlab.ntua.gr
SUMMARY:Tech Talk #6 - Unlocking the potentials of future computing systems: SIU Embedded Systems Software Lab
DESCRIPTION:Την Παρασκευή 27/11/2020 και ώρα 15:00 EET (Greek Time) θα έχουμε την παρουσίαση για τα Fridays Tech Talks από τον πρώην Ph.D.\, Post Doc στο microlab και νυν καθηγητή στο Southern Illinois University\, Ηρακλή Αναγνωστόπουλου με τίτλο: \n\n“Unlocking the potentials of future computing systems: SIU Embedded Systems Software Lab” \n\nΗ παρουσίαση θα γίνει μέσω webex στο παρακάτω link Webex.
URL:https://microlab.ntua.gr/event/tech-talk-6-unlocking-the-potentials-of-future-computing-systems-siu-embedded-systems-software-lab/
CATEGORIES:Tech Talks
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Moscow:20201120T173000
DTEND;TZID=Europe/Moscow:20201120T190000
DTSTAMP:20201118T154049Z
CREATED:20201118T134137Z
LAST-MODIFIED:20201118T154049Z
UID:5020-1605893400-1605898800@microlab.ntua.gr
SUMMARY:Tech Talk #5 – Πώς η καινοτομία δημιουργεί ΙΣΤΟΡΙΑ; Το παράδειγμα  του MicroLab: παρελθόν\, παρόν και μέλλον
DESCRIPTION:Την Παρασκευή 20/11/2020 και ώρα 17:30 EET (Greek Time) θα έχουμε την παρουσίαση για τα Fridays Tech Talks από τον καθηγητή Δημήτριο Σούντρη με τίτλο: \n\n“Πώς η καινοτομία δημιουργεί ΙΣΤΟΡΙΑ; Το παράδειγμα του MicroLab: παρελθόν\, παρόν και μέλλον” \n\nΗ παρουσίαση θα γίνει μέσω webex στο παρακάτω link Webex.
URL:https://microlab.ntua.gr/event/tech-talk-5-%cf%80%cf%8e%cf%82-%ce%b7-%ce%ba%ce%b1%ce%b9%ce%bd%ce%bf%cf%84%ce%bf%ce%bc%ce%af%ce%b1-%ce%b4%ce%b7%ce%bc%ce%b9%ce%bf%cf%85%cf%81%ce%b3%ce%b5%ce%af-%ce%b9%cf%83%cf%84%ce%bf/
CATEGORIES:Tech Talks
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Moscow:20201113T100000
DTEND;TZID=Europe/Moscow:20201113T113000
DTSTAMP:20201209T141244Z
CREATED:20201110T092850Z
LAST-MODIFIED:20201209T141244Z
UID:5013-1605261600-1605267000@microlab.ntua.gr
SUMMARY:Tech Talk #4 - From DRAM to NVM: Technologies & Challenges
DESCRIPTION:Την Παρασκευή 13/11/2020 και ώρα 10:00 EET (Greek Time) θα έχουμε την παρουσίαση για τα Fridays Tech Talks από τον υποψήφιο διδάκτορα Μανώλη Κατσαραγάκη με τίτλο: \n\n“From DRAM to NVM: Technologies & Challenges” \n\nΗ παρουσίαση θα γίνει μέσω webex στο παρακάτω link Webex. \n  \nDownload PDF slides
URL:https://microlab.ntua.gr/event/tech-talk-4/
CATEGORIES:Tech Talks
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Moscow:20201106T100000
DTEND;TZID=Europe/Moscow:20201106T233000
DTSTAMP:20201209T141209Z
CREATED:20201103T100627Z
LAST-MODIFIED:20201209T141209Z
UID:5005-1604656800-1604705400@microlab.ntua.gr
SUMMARY:Tech Talk #3 - Serverless Computing: Micromanagement on the Clouds
DESCRIPTION:Την Παρασκευή 6/11/2020 και ώρα 10:00 EEST (Greek Time) θα έχουμε την παρουσίαση για τα Fridays Tech Talks από τον υποψήφιο διδάκτορα Αχιλλέα Τζενετόπουλο με τίτλο: \n\n“Serverless Computing: Micromanagement on the Clouds” \n\nΗ παρουσίαση θα γίνει μέσω webex στο παρακάτω link Webex. \n  \nDownload PDF slides
URL:https://microlab.ntua.gr/event/microlabs-fridays-tech-talks-3/
CATEGORIES:Tech Talks
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BEGIN:VEVENT
DTSTART;TZID=Europe/Moscow:20201030T100000
DTEND;TZID=Europe/Moscow:20201030T113000
DTSTAMP:20201110T092627Z
CREATED:20201026T153654Z
LAST-MODIFIED:20201110T092627Z
UID:4991-1604052000-1604057400@microlab.ntua.gr
SUMMARY:Tech Talk #2 - NLP through years and hardware accelerators
DESCRIPTION:Την Παρασκευή 30/10/2020 και ώρα 10:00 EEST (Greek Time) θα έχουμε την δεύτερη παρουσίαση για τα Fridays Tech Talks από τον υποψήφιο διδάκτορα Γεώργιο Τζάνο με τίτλο: \n\n“NLP through years and hardware accelerators” \n\nΗ παρουσίαση θα γίνει μέσω webex στο παρακάτω link Webex.
URL:https://microlab.ntua.gr/event/microlabs-fridays-tech-talks-2/
CATEGORIES:Tech Talks
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Moscow:20201023T100000
DTEND;TZID=Europe/Moscow:20201023T110000
DTSTAMP:20201110T092643Z
CREATED:20201012T091646Z
LAST-MODIFIED:20201110T092643Z
UID:4973-1603447200-1603450800@microlab.ntua.gr
SUMMARY:Tech Talk #1 - Energy-Optimal Computing in the AI Age: Where We Are\, Where Can We Go
DESCRIPTION:Την Παρασκευή 23/10/2020 και ώρα 10:00 EEST (Greek Time) θα έχουμε την πρώτη παρουσίαση για τα Fridays Tech Talks από τον υποψήφιο διδάκτορα Χρήστο Λαμπράκο με τίτλο: \n\n“Energy-Optimal Computing in the AI Age: Where We Are\, Where Can We Go” \n\nΗ παρουσίαση θα γίνει μέσω webex στο παρακάτω link Webex. \n  \nDownload PDF slides
URL:https://microlab.ntua.gr/event/microlabs-fridays-tech-talks-1/
CATEGORIES:Tech Talks
ORGANIZER;CN="Christos Labrakos":MAILTO:cplamprakos@microlab.ntua.gr
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20191217T160000
DTEND;TZID=UTC:20191217T180000
DTSTAMP:20191216T125836Z
CREATED:20191216T125702Z
LAST-MODIFIED:20191216T125836Z
UID:4863-1576598400-1576605600@microlab.ntua.gr
SUMMARY:Ημερίδα για Διπλωματικές Εργασίες 2019-2020\, 17/12/19\, 16:00
DESCRIPTION:Την Τρίτη 17 Δεκεμβρίου 2019 ώρα 16:00 στο Εργαστήριο Μικροϋπολογιστών & Ψηφιακών Συστημάτων\, Νέα Κτίρια ΗΜΜΥ αίθουσα Β1.20 θα λάβει χώρα εκδήλωση που αφορά την ενημέρωση των φοιτητών για τις ερευνητικές δραστηριότητες και τα προτεινόμενα θέματα διπλωματικών του εργαστηρίου Μικροϋπολογιστών & Ψηφιακών Συστημάτων.\n\nΤα θέματα των διπλωματικών μπορείτε να τα βρείτε εδώ https://microlab.ntua.gr/master-bachelor-theses/\nΤο πρόγραμμα της εκδήλωσης:\n16:00 – 16:15 Εισαγωγή Καθ. Δημήτριος Σούντρης\n16:15 – 16:30 Reconfigurable Computing / Space applications Δημήτρης Δανόπουλος\n16:30 – 16:45 Machine Learning Χρήστος Λαμπράκος\n16:45 – 17:00 Computational Neuroscience Δρ. Χαράλαμπος Σιδηρόπουλος\n17:00 – 17:15 Cloud Computing Δημοσθένης Μασούρος\n17:15 – 17:30 Embedded Systems & IoT Κατσαραγάκης Μανώλης\n17:30 – 17:45 Cyberphysical Systems Χαράλαμπος Μάραντος
URL:https://microlab.ntua.gr/event/%ce%b7%ce%bc%ce%b5%cf%81%ce%af%ce%b4%ce%b1-%ce%b3%ce%b9%ce%b1-%ce%b4%ce%b9%cf%80%ce%bb%cf%89%ce%bc%ce%b1%cf%84%ce%b9%ce%ba%ce%ad%cf%82-%ce%b5%cf%81%ce%b3%ce%b1%cf%83%ce%af%ce%b5%cf%82-2019-2020-17-12/
ATTACH;FMTTYPE=image/png:https://microlab.ntua.gr/wp-content/uploads/2019/12/mlab-dipl-header.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20190628T150000
DTEND;TZID=UTC:20190628T180000
DTSTAMP:20190621T073238Z
CREATED:20190621T073238Z
LAST-MODIFIED:20190621T073238Z
UID:4757-1561734000-1561744800@microlab.ntua.gr
SUMMARY:Embedded Systems Undergraduate Finalists Exams
DESCRIPTION:Καλησπέρα\, \nΗ επί πτυχίω εξέταση για το μάθημα “Ενσωματωμένα Συστήματα” θα πραγματοποιηθεί την  Παρασκευή 28 Ιουνίου 2019 – 15:00-18:00\, στην αίθουσα Β1.14\, Νέα κτίρια Ηλεκτρολόγων. \nΚαλή  επιτυχία.
URL:https://microlab.ntua.gr/event/embedded-systems-undergraduate-finalists-exams/
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BEGIN:VEVENT
DTSTART;TZID=UTC:20190612T133000
DTEND;TZID=UTC:20190612T170000
DTSTAMP:20190612T075231Z
CREATED:20190403T134939Z
LAST-MODIFIED:20190612T075231Z
UID:2047-1560346200-1560358800@microlab.ntua.gr
SUMMARY:Παρουσίαση Διδακτορικού Κων/νου Μαραγκού
DESCRIPTION:Την Τετάρτη 12/06/2019\, στην Αιθουσα Συνεδριάσεων της Σχολής (ισογειο\,  Νεο Κτιριο Ηλεκτρολόγων Μηχ.) και ώρα 13:30 θα γινει παρουσίαση της διδακτορικής διατριβής  του κου Κων/νου Μαραγκού ενώπιον της  7μελούς εξεταστικής επιτροπής με τίτλο: \n“Exploitation of Process Variability in FPGAs Devices” \nΑκολουθεί Extended Abstract. \nTransistor scaling is one of the major factors driving the continuous advancements in performance of semiconductor chips. However\, as transistors’ size reach the atomic scale\, the manufacturing process becomes increasingly challenging and inefficient from an economic standpoint. The industry struggles to keep up with Moore’s law\, while the speed and power gains arise as we move from one technology node to the next are reduced compared to past trends. To alleviate this performance gap\, alternative solutions have been proposed including heterogeneous computing\, more efficient architectures\, 3D technology\, in-memory computing\, etc. In this context\, one of the contributions of the current research work\, relies on the presentation of HW accelerators based on FPGA platforms for improved performance figures. \nWe describe design methodologies for the development of efficient architectures based on sophisticated parallelization methods\, design space explorations and a custom HW partitioning methodology for multi-FPGA systems. We demonstrate the benefits arise by the aforementioned methodologies on multiple application fields considering diverse FPGA platforms; conventional\, SoC- and multi-FPGAs. Another challenge which becomes more significant with further technology scaling is the mitigation of major reliability issues\, such as process variability\, voltage drop effects and thermal dissipation. To cope with the aforementioned issues and provide acceptable solutions\, the chip vendors impose global and conservative guard-bands in the operation of their manufactured chips. The guard-bands are defined according to the extreme-case process corners of the manufactured chips. Such pessimistic strategy\, however\, do not exploit the actual performance capabilities of the individual chips and do not adapt to those operating conditions (e.g.\, IR-drop) that strongly depend upon the individual characteristics of an application. Therefore\, significant performance is lost\, either in terms of frequency or power consumption. \nIn the current research work\, our core contribution is based on the delivery of adaptive solutions with respect to the quality of the underlying silicon and the specifics of the application running on the chip. We specifically target on the performance enhancement of present-day and future FPGA-based processing systems. We begin with the presentation of a methodology for the evaluation of process variability in commercial off-the-shelf FPGA devices. The proposed methodology is based on the generation of variability maps characterizing in a fine-grain resolution the performance variation across the FPGA fabric. Utilizing the proposed methodology\, we provide variability results considering multiple and of diverse types (conventional\, SoC) 28nm FPGA devices. We evaluate the impact of variability on larger realistic designs and establish the usage of variability maps as performance prediction tools. Motivated by the performance gains arise by the exploitation of process variability and operation guard-bands\, we introduce a\nframework for the delivery of more efficient solutions in terms of frequency and/or voltage. The proposed framework bases on variability maps for the mapping of a given design to the most efficient region\n(intra-die) and device (inter-die)\, as well as frequency and voltage scaling methods to tune the FPGA operation with respect to user requirements. \nThe main advantages of the proposed framework compared to prior art\, are the exploitation of process variability for improved performance gains and its application at user level\, without requiring the modification of CAD’s tool or design netlist. Depending on the underlying device(s) and the given application\, the proposed framework is able to deliver even 2x better performance compared to that of STA estimations. \nΗ παρουσία σας θα μας ειναι ιδιαίτερα τιμητική. \nΜε Εκτίμηση\,\nΔημ. Σούντρης
URL:https://microlab.ntua.gr/event/%cf%80%ce%b1%cf%81%ce%bf%cf%85%cf%83%ce%af%ce%b1%cf%83%ce%b7/
CATEGORIES:test
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