Specifically, Dimitrios Danopoulos received the first price on the compute acceleration category in Xilinx OpenHW 2021 competition. In this project, they implemented an image reconstruction algorithm with Deep Learning, specifically with GANs (Generative Adversarial Networks). They trained and accelerated a Generator model in a Cloud FPGA (Alveo U50 FPGA) which was capable of reconstructing images of clothing with high speed and power efficiency.

The work has been done under the project “CloudAccel: Hardware Acceleration of Machine Learning Applications in the Cloud” that has received funding from the Hellenic Foundation for Research and Innovation (HFRI) and the Genal Secretariat for Research and Technology (GSRT) under grant agreement no 2212 and Xilinx University Program.

It’s worth mentioning that for this award in the competition, Xilinx will donate a high-performance FPGA (Alveo family) to Microprocessors Lab.

The project is available on GitHub:

https://github.com/cloudaccel/gan-hls

A video showing the main novelties is shown here:

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Τα θέματα των διπλωματικών εργασιών που παρουσιάστηκαν κατηγοριοποιούνται στους ακόλουθους τομείς:
– Reconfigurable Computing
– Approximate Computing: Circuits and Accelerators
– Embedded systems and Internet of Things
– Cloud Computing
– High Performance Computing and Accelerators
– Sustainability and Green Computing
– Embedded Computing in Space: Applications and Platforms

Πιο αναλυτικές πληροφορίες μπορείτε να βρείτε εδώ: https://microlab.ntua.gr/master-bachelor-theses/

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Specifically, the project which is called “COVID4HPC” was developed in the Microprocessors and Digital Systems Laboratory (MicroLab) of ECE NTUA. The project aims to identify COVID disease in chest X-Rays from patients using FPGAs with great speed and accuracy. A very useful application that can help doctors in hospitals or clinics in their medical diagnosis in the pandemic era. Below you can check the presentation of the winners by Ivo Bolsens, the Senior Vice President and Chief Technology Officer of Xilinx.

https://www.linkedin.com/posts/xilinx_xilinx-adaptive-computing-challenge-winners-activity-6757352168560320512-mSET

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https://2019.spaceappschallenge.org/challenges/earths-oceans/rising-water/teams/ugrace-anatomy/project

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Specifically, Dimitris Danopoulos received the first price on the hardware acceleration category for his work on the acceleration of FAISS; a widely used application for efficient similarity search and clustering of dense vectors in a Xilinx Alveo FPGA board and cloud FPGA. George Tzanos received the first price on the pynq category (using the Zynq SoC) for the efficient acceleration of the Naïve Bayes algorithm for training and classification.

The work has been done under the project “CloudAccel: Hardware Acceleration of Machine Learning Applications in the Cloud” that has received funding from the Hellenic Foundation for Research and Innovation (HFRI) and the Genal Secretariat for Research and Technology (GSRT) under grant agreement no 2212 and Xilinx University Program.

It worth notice that in 2017 students from the Microlab/NTUA had also received the first prize on this contest and later established the InAccel startup that is now a world-leader on applications acceleration using FPGAs.

The platforms are available on github:

https://github.com/dimdano/faiss-fpga

https://github.com/AcceleratedCloud/SDSoC/tree/master/Gaussian%20NaiveBayes

A video showing the main novelties of this platform is shown here:

https://www.youtube.com/watch?v=a7iEHEheDxs

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Extended Abstract:

Transistor scaling is one of the major factors driving the continuous advancements in performance of semiconductor chips. However, as transistors’ size reach the atomic scale, the manufacturing process becomes increasingly challenging and inefficient from an economic standpoint. The industry struggles to keep up with Moore’s law, while the speed and power gains arise as we move from one technology node to the next are reduced compared to past trends. To alleviate this performance gap, alternative solutions have been proposed including heterogeneous computing, more efficient architectures, 3D technology, in-memory computing, etc. In this context, one of the contributions of the current research work, relies on the presentation of HW accelerators based on FPGA platforms for improved performance figures. We describe design methodologies for the development of efficient architectures based on sophisticated parallelization methods, design space explorations and a custom HW partitioning methodology for multi-FPGA systems. We demonstrate the benefits arise by the aforementioned methodologies on multiple application fields considering diverse FPGA platforms; conventional, SoC- and multi-FPGAs. Another challenge which becomes more significant with further technology scaling is the mitigation of major reliability issues, such as process variability, voltage drop effects and thermal dissipation. To cope with the aforementioned issues and provide acceptable solutions, the chip vendors  impose global and conservative guard-bands in the operation of their manufactured chips. The guard-bands are defined according to the extreme-case process corners of the manufactured chips. Such pessimistic strategy, however, do not exploit the actual performance capabilities of the individual chips and do not adapt to those operating conditions (e.g., IR-drop) that strongly depend upon the individual characteristics of an application. Therefore, significant performance is lost, either in terms of frequency or power consumption. In the current research work, our core contribution is based on the delivery of adaptive solutions with respect to the quality of the underlying silicon and the specifics of the application running on the chip. We specifically target on the performance enhancement of present-day and future FPGA-based processing systems. We begin with the presentation of a methodology for the evaluation of process variability in commercial off-the-shelf FPGA devices. The proposed methodology is based on the generation of variability maps characterizing in a fine-grain resolution the performance variation across the FPGA fabric. Utilizing the proposed methodology, we provide variability results considering multiple and of diverse types (conventional, SoC) 28nm FPGA devices. We evaluate the impact of variability on larger realistic designs and establish the usage of variability maps as performance prediction tools. Motivated by the performance gains arise by the exploitation of process variability and operation guard-bands, we introduce a framework for the delivery of more efficient solutions in terms of frequency and/or voltage. The proposed framework bases on variability maps for the mapping of a given design to the most efficient region (intra-die) and device (inter-die), as well as frequency and voltage scaling methods to tune the FPGA operation with respect to user requirements. The main advantages of the proposed framework compared to prior art, are the exploitation of process variability for improved performance gains and its application at user level, without requiring the modification of CAD’s tool or design netlist. Depending on the underlying device(s) and the given application, the proposed framework is able to deliver even 2x better performance compared to that of STA estimations.

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Cooperative Arithmetic-Aware Approximation Techniques for Energy-Efficient Multipliers Abstract:

Approximate computing appears as an emerging and promising solution for energy-efficient system designs, exploiting the inherent error-tolerant nature of various applications. In this paper, targeting multiplication circuits, i.e., the energy-hungry counterpart of hardware accelerators, an extensive exploration of the error–energy trade-off, when combining arithmetic-level approximation techniques, is performed for the first time. Arithmetic-aware approximations deliver significant energy reductions, while allowing to control the error values with discipline by setting accordingly a configuration parameter. Inspired from the promising results of prior works with one configuration parameter, we propose 5 hybrid design families for approximate and energy-friendly hardware multipliers, consisting of two independent parameters to tune the approximation levels. Interestingly, the resolution of the state-of-the-art Pareto diagram is improved, giving the flexibility to achieve better energy gains for a specific error constraint imposed by the system. Moreover, we outperform prior works in the field of approximate multipliers by up to 60% energy reduction, and thus, we define the new Pareto front.

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More information: https://sdk4ed.eu/news/

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